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    SEMICONDUCTOR STRUCTURE AND SEMICONDUCTOR PATTERN STRUCTURE
    2.
    发明申请
    SEMICONDUCTOR STRUCTURE AND SEMICONDUCTOR PATTERN STRUCTURE 有权
    半导体结构和半导体图案结构

    公开(公告)号：US20160148878A1

    公开(公告)日：2016-05-26

    申请号：US14583575

    申请日：2014-12-26

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Shin-Chi Chen ,  Chih-Yueh Li ,  Pei-Ching Yeh ,  Chih-Jen Lin

    IPC: H01L23/00 ,  H01L29/06 ,  H01L29/78

    CPC classification number: H01L29/0653 ,  H01L21/28123 ,  H01L21/76224 ,  H01L29/78

    Abstract: A semiconductor pattern structure includes a substrate, an input/output (I/O) region defined on the substrate, a core region defined on the substrate, a dummy region defined on the substrate, and a gate electrode formed on the substrate. The dummy region is formed between the I/O region and the core region. The gate electrode crosses the I/O region and covers a portion of the dummy region.

    Abstract translation: 半导体图案结构包括基板，限定在基板上的输入/输出（I / O）区域，限定在基板上的芯区域，限定在基板上的虚拟区域和形成在基板上的栅电极。 在I / O区域和核心区域之间形成虚拟区域。 栅电极与I / O区域交叉并覆盖虚拟区域的一部分。

    Semiconductor device having metal gate and manufacturing method thereof
    3.
    发明授权
    Semiconductor device having metal gate and manufacturing method thereof 有权
    具有金属栅极的半导体器件及其制造方法

    公开(公告)号：US08952451B2

    公开(公告)日：2015-02-10

    申请号：US14135588

    申请日：2013-12-20

    Applicant: United Microelectronics Corp.

    Inventor： Po-Jui Liao ,  Tsung-Lung Tsai ,  Chien-Ting Lin ,  Shao-Hua Hsu ,  Yeng-Peng Wang ,  Chun-Hsien Lin ,  Chan-Lon Yang ,  Guang-Yaw Hwang ,  Shin-Chi Chen ,  Hung-Ling Shih ,  Jiunn-Hsiung Liao ,  Chia-Wen Liang

    IPC: H01L29/66 ,  H01L29/78 ,  H01L21/8238

    CPC classification number: H01L29/78 ,  H01L21/823842 ,  H01L21/82385 ,  H01L29/66545

    Abstract: A semiconductor device having a metal gate includes a substrate having a first gate trench and a second gate trench formed thereon, a gate dielectric layer respectively formed in the first gate trench and the second gate trench, a first work function metal layer formed on the gate dielectric layer in the first gate trench and the second gate trench, a second work function metal layer respectively formed in the first gate trench and the second gate trench, and a filling metal layer formed on the second work function metal layer. An opening width of the second gate trench is larger than an opening width of the first gate trench. An upper area of the second work function metal layer in the first gate trench is wider than a lower area of the second work function metal layer in the first gate trench.

    Abstract translation: 具有金属栅极的半导体器件包括具有形成在其上的第一栅极沟槽和第二栅极沟槽的衬底，分别形成在第一栅极沟槽和第二栅极沟槽中的栅极电介质层，形成在栅极上的第一功函数金属层 第一栅极沟槽和第二栅极沟槽中的介电层，分别形成在第一栅极沟槽和第二栅极沟槽中的第二功函数金属层和形成在第二功函数金属层上的填充金属层。 第二栅极沟槽的开口宽度大于第一栅极沟槽的开口宽度。 第一栅极沟槽中的第二功函数金属层的上部区域比第一栅极沟槽中的第二功函数金属层的下部区域宽。

    STRAINED SILICON STRUCTURE
    4.
    发明申请
    STRAINED SILICON STRUCTURE 有权
    应变硅结构

    公开(公告)号：US20130292775A1

    公开(公告)日：2013-11-07

    申请号：US13936214

    申请日：2013-07-08

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Guang-Yaw Hwang ,  Ling-Chun Chou ,  I-Chang Wang ,  Shin-Chuan Huang ,  Jiunn-Hsiung Liao ,  Shin-Chi Chen ,  Pau-Chung Lin ,  Chiu-Hsien Yeh ,  Chin-Cheng Chien ,  Chieh-Te Chen

    IPC: H01L27/088

    CPC classification number: H01L27/088 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/7848

    Abstract: A strained silicon substrate structure includes a first transistor and a second transistor disposed on a substrate. The first transistor includes a first gate structure and two first source/drain regions disposed at two sides of the first gate structure. A first source/drain to gate distance is between each first source/drain region and the first gate structure. The second transistor includes a second gate structure and two source/drain doped regions disposed at two side of the second gate structure. A second source/drain to gate distance is between each second source/drain region and the second gate structure. The first source/drain to gate distance is smaller than the second source/drain to gate distance.

    Abstract translation: 应变硅衬底结构包括设置在衬底上的第一晶体管和第二晶体管。 第一晶体管包括第一栅极结构和设置在第一栅极结构的两侧的两个第一源极/漏极区域。 第一源极/漏极到栅极间距在每个第一源极/漏极区域和第一栅极结构之间。 第二晶体管包括第二栅极结构和设置在第二栅极结构的两侧的两个源极/漏极掺杂区域。 第二源极/漏极到栅极间距在每个第二源极/漏极区域和第二栅极结构之间。 第一源极/漏极到栅极距离小于第二源极/漏极到栅极距离。

    SEMICONDUCTOR STRUCTURE
    6.
    发明申请
    SEMICONDUCTOR STRUCTURE 有权

    公开(公告)号：US20230136978A1

    公开(公告)日：2023-05-04

    申请号：US17534419

    申请日：2021-11-23

    Applicant: United Microelectronics Corp.

    Inventor： Chun-Chi Huang ,  Hui-Lung Chou ,  Chuang-Han Hsieh ,  Yung-Feng Lin ,  Shin-Chi Chen

    IPC: H01L23/00 ,  H01L23/528

    Abstract: A semiconductor structure including a substrate, a dielectric layer, a first conductive layer, and a passivation layer is provided. The dielectric layer is disposed on the substrate. The first conductive layer is disposed on the dielectric layer. The passivation layer is disposed on the first conductive layer and the dielectric layer. The passivation layer includes a first upper surface and a second upper surface. The first upper surface is located above a top surface of the first conductive layer. The second upper surface is located on one side of the first conductive layer. A height of the first upper surface is higher than a height of the second upper surface. The height of the second upper surface is lower than or equal to a height of a lower surface of the first conductive layer located between a top surface of the dielectric layer and the first conductive layer.

    METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
    8.
    发明申请
    METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 有权
    制造半导体器件的方法

    公开(公告)号：US20150380312A1

    公开(公告)日：2015-12-31

    申请号：US14314425

    申请日：2014-06-25

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Shin-Chi Chen ,  Chih-Yueh Li ,  Shui-Yen Lu ,  Chi-Mao Hsu ,  Yuan-Chi Pai ,  Yu-Hong Kuo ,  Nien-Ting Ho

    IPC: H01L21/8238 ,  H01L21/28 ,  H01L29/423 ,  H01L21/311

    CPC classification number: H01L21/82385 ,  H01L21/28026 ,  H01L21/28088 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/823842 ,  H01L29/42376 ,  H01L29/66545

    Abstract: A method of manufacturing a semiconductor device is provided. The method includes the following steps. A substrate including a first transistor having a first conductivity type, a second transistor having a second conductivity type and a third transistor having the first conductivity type is formed. An inner-layer dielectric layer is formed on the substrate, and includes a first gate trench corresponding to the first transistor, a second gate trench corresponding to the second transistor and a third gate trench corresponding to the third transistor. A work function metal layer is formed on the inner-layer dielectric layer. An anti-reflective layer is coated on the work function metal layer. The anti-reflective layer on the second transistor and on the top portion of the third gate trench is removed to expose the work function metal layer. The exposed work function metal layer is removed.

    Abstract translation: 提供一种制造半导体器件的方法。 该方法包括以下步骤。 形成包括具有第一导电类型的第一晶体管，具有第二导电类型的第二晶体管和具有第一导电类型的第三晶体管的衬底。 内层电介质层形成在衬底上，并且包括对应于第一晶体管的第一栅极沟槽，对应于第二晶体管的第二栅极沟槽和对应于第三晶体管的第三栅极沟槽。 在内层电介质层上形成功函数金属层。 在功函数金属层上涂敷抗反射层。 去除第二晶体管上的抗反射层和第三栅极沟槽的顶部以暴露功函数金属层。 暴露的功能金属层被去除。

    METHOD FOR REMOVING NITRIDE MATERIAL
    9.
    发明申请
    METHOD FOR REMOVING NITRIDE MATERIAL 有权
    去除氮化物的方法

    公开(公告)号：US20140256151A1

    公开(公告)日：2014-09-11

    申请号：US13784846

    申请日：2013-03-05

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chi-Sheng Chen ,  Shin-Chi Chen ,  Chih-Yueh Li ,  Ted Ming-Lang Guo ,  Bo-Syuan Lee ,  Tsung-Hsun Tsai ,  Yu-Chin Cheng

    IPC: H01L21/308

    CPC classification number: H01L21/308 ,  H01L21/31111 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659

    Abstract: A method for removing silicon nitride material includes following steps. A substrate having at least a gate structure formed thereon is provided, and at least a silicon nitride hard mask is formed on top of the gate structure. A first removal is performed to remove a portion of the silicon nitride hard mask with a first phosphoric acid (H3PO4) solution. A second removal is subsequently performed to remove remnant silicon nitride hard mask with a second phosphoric acid solution. The first removal and the second removal are performed in-situ. A temperature of the second phosphoric acid solution is lower than a temperature of the first phosphoric acid solution.

    Abstract translation: 一种除去氮化硅材料的方法包括以下步骤。 提供了至少形成有栅极结构的衬底，并且在栅极结构的顶部上形成至少一个氮化硅硬掩模。 执行第一次去除以用第一磷酸（H 3 PO 4）溶液去除一部分氮化硅硬掩模。 随后进行第二次去除以用第二种磷酸溶液去除残留的氮化硅硬掩模。 第一次去除和第二次去除是原位进行的。 第二磷酸溶液的温度低于第一磷酸溶液的温度。

    SEMICONDUCTOR DEVICE HAVING METAL GATE AND MANUFACTURING METHOD THEREOF
    10.
    发明申请
    SEMICONDUCTOR DEVICE HAVING METAL GATE AND MANUFACTURING METHOD THEREOF 有权
    具有金属门的半导体器件及其制造方法

    公开(公告)号：US20140127892A1

    公开(公告)日：2014-05-08

    申请号：US14135520

    申请日：2013-12-19

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Po-Jui Liao ,  Tsung-Lung Tsai ,  Chien-Ting Lin ,  Shao-Hua Hsu ,  Yeng-Peng Wang ,  Chun-Hsien Lin ,  Chan-Lon Yang ,  Guang-Yaw Hwang ,  Shin-Chi Chen ,  Hung-Ling Shih ,  Jiunn-Hsiung Liao ,  Chia-Wen Liang

    IPC: H01L21/8238

    CPC classification number: H01L29/78 ,  H01L21/823842 ,  H01L21/82385 ,  H01L29/66545

    Abstract: A method of manufacturing a semiconductor device having metal gate includes providing a substrate having a first transistor and a second transistor formed thereon, the first transistor having a first gate trench formed therein, forming a first work function metal layer in the first gate trench, forming a sacrificial masking layer in the first gate trench, removing a portion of the sacrificial masking layer to expose a portion of the first work function metal layer, removing the exposed first function metal layer to form a U-shaped work function metal layer in the first gate trench, and removing the sacrificial masking layer. The first transistor includes a first conductivity type and the second transistor includes a second conductivity type. The first conductivity type and the second conductivity type are complementary.

    Abstract translation: 一种制造具有金属栅极的半导体器件的方法包括：提供具有形成在其上的第一晶体管和第二晶体管的衬底，所述第一晶体管具有形成在其中的第一栅极沟槽，在所述第一栅极沟槽中形成第一功函数金属层， 在第一栅极沟槽中的牺牲掩模层，去除牺牲掩模层的一部分以暴露第一功函数金属层的一部分，去除暴露的第一功能金属层，以在第一栅极沟槽中的第一栅极沟槽中形成U形功函数金属层 栅极沟槽，以及去除牺牲掩模层。 第一晶体管包括第一导电类型，第二晶体管包括第二导电类型。 第一导电类型和第二导电类型是互补的。

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