公开(公告)号：US10340230B1

公开(公告)日：2019-07-02

申请号：US15847567

申请日：2017-12-19

Applicant: United Microelectronics Corp.

Inventor： Tsong-Lin Shen ,  Chen-Hsiao Wang ,  Sheng-Wei Hung ,  Chin-Tsai Chang ,  Hui-Lung Chou

IPC: H01L23/528 ,  H01L23/00 ,  H01L23/532

Abstract: A semiconductor chip is provided. The semiconductor chip includes at least one interlayer dielectric layer, a transmission pattern and a stress absorption structure. The at least one interlayer dielectric layer is disposed on a substrate. The transmission pattern is disposed on the at least one interlayer dielectric layer and within a peripheral region of the semiconductor chip. The transmission pattern is electrically connected to an external signal source. The stress absorption structure is disposed in the at least one interlayer dielectric layer within the peripheral region, and electrically connected to the transmission pattern. The stress absorption structure is covered by the transmission pattern.

公开(公告)号：US11764174B2

公开(公告)日：2023-09-19

申请号：US17534419

申请日：2021-11-23

Applicant: United Microelectronics Corp.

Inventor： Chun-Chi Huang ,  Hui-Lung Chou ,  Chuang-Han Hsieh ,  Yung-Feng Lin ,  Shin-Chi Chen

IPC: H01L21/00 ,  H01L23/00 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L24/02 ,  H01L23/528 ,  H01L24/05 ,  H01L23/53295 ,  H01L2224/0219 ,  H01L2224/02181 ,  H01L2224/02185 ,  H01L2224/05557

Abstract: A semiconductor structure including a substrate, a dielectric layer, a first conductive layer, and a passivation layer is provided. The dielectric layer is disposed on the substrate. The first conductive layer is disposed on the dielectric layer. The passivation layer is disposed on the first conductive layer and the dielectric layer. The passivation layer includes a first upper surface and a second upper surface. The first upper surface is located above a top surface of the first conductive layer. The second upper surface is located on one side of the first conductive layer. A height of the first upper surface is higher than a height of the second upper surface. The height of the second upper surface is lower than or equal to a height of a lower surface of the first conductive layer located between a top surface of the dielectric layer and the first conductive layer.

公开(公告)号：US20230136978A1

公开(公告)日：2023-05-04

申请号：US17534419

申请日：2021-11-23

Applicant: United Microelectronics Corp.

Inventor： Chun-Chi Huang ,  Hui-Lung Chou ,  Chuang-Han Hsieh ,  Yung-Feng Lin ,  Shin-Chi Chen

IPC: H01L23/00 ,  H01L23/528

Abstract: A semiconductor structure including a substrate, a dielectric layer, a first conductive layer, and a passivation layer is provided. The dielectric layer is disposed on the substrate. The first conductive layer is disposed on the dielectric layer. The passivation layer is disposed on the first conductive layer and the dielectric layer. The passivation layer includes a first upper surface and a second upper surface. The first upper surface is located above a top surface of the first conductive layer. The second upper surface is located on one side of the first conductive layer. A height of the first upper surface is higher than a height of the second upper surface. The height of the second upper surface is lower than or equal to a height of a lower surface of the first conductive layer located between a top surface of the dielectric layer and the first conductive layer.

公开(公告)号：US20190189568A1

公开(公告)日：2019-06-20

申请号：US15847567

申请日：2017-12-19

Applicant: United Microelectronics Corp.

Inventor： Tsong-Lin Shen ,  Chen-Hsiao Wang ,  Sheng-Wei Hung ,  Chin-Tsai Chang ,  Hui-Lung Chou

IPC: H01L23/00 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L23/562 ,  H01L23/528 ,  H01L23/5329 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/02381 ,  H01L2224/0401

Abstract: A semiconductor chip is provided. The semiconductor chip includes at least one interlayer dielectric layer, a transmission pattern and a stress absorption structure. The at least one interlayer dielectric layer is disposed on a substrate. The transmission pattern is disposed on the at least one interlayer dielectric layer and within a peripheral region of the semiconductor chip. The transmission pattern is electrically connected to an external signal source. The stress absorption structure is disposed in the at least one interlayer dielectric layer within the peripheral region, and electrically connected to the transmission pattern. The stress absorption structure is covered by the transmission pattern.

公开(公告)号：US20230326882A1

公开(公告)日：2023-10-12

申请号：US17735099

申请日：2022-05-02

Applicant: United Microelectronics Corp.

Inventor： Hui-Lung Chou ,  Ching-Li Yang ,  Chih-Sheng Chang ,  Chien-Ting Lin

IPC: H01L23/00 ,  H01L23/58

CPC classification number: H01L23/564 ,  H01L23/562 ,  H01L23/585

Abstract: A semiconductor structure and its manufacturing method are provided. The semiconductor structure includes a substrate, a first dielectric layer on the substrate, a second dielectric layer on the first dielectric layer, a seal ring structure including first and second interconnect structures, and a passivation layer on the seal ring structure and the second dielectric layer. The first interconnect structure is located in the first dielectric layer. The second interconnect structure is located in the second dielectric layer and connected to the first interconnect structure. The passivation layer has a spacer portion covering a sidewall of the second dielectric layer and a portion of the first dielectric layer. A ditch exists in the passivation layer and the first dielectric layer. The spacer portion is located between the ditch and the seal ring structure. The semiconductor structure is able to reduce time and power of an etching process for forming the ditch.