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    WAFER WITH TEST STRUCTURE AND METHOD OF DICING WAFER
    3.
    发明公开
    WAFER WITH TEST STRUCTURE AND METHOD OF DICING WAFER 审中-公开

    公开(公告)号：US20240170332A1

    公开(公告)日：2024-05-23

    申请号：US18420779

    申请日：2024-01-24

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Wei-Ren Huang ,  Chen-Hsiao Wang ,  Kai-Kuang Ho

    IPC: H01L21/78 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/311 ,  H01L21/66

    CPC classification number: H01L21/78 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/31144 ,  H01L22/32

    Abstract: A wafer with a test structure includes a wafer with a front side and a back side. A first die, a second die, a third die and a scribe line are disposed on the wafer. The scribe line is positioned between the dice. The first die includes a first dielectric layer and a first metal connection disposed within and on the first dielectric layer. A test structure and a dielectric layer are disposed on the scribe line, wherein the test structure is on the dielectric layer. Two first trenches are respectively disposed between the first dielectric layer and the dielectric layer and disposed at one side of the dielectric layer. Two second trenches penetrate the wafer, and each of the two second trenches respectively connects to a corresponding one of the two first trenches. A grinding tape covers the front side of the wafer and contacts the test structure.

    THREE-DIMENSIONAL INTEGRATED CIRCUIT STRUCTURE
    6.
    发明申请
    THREE-DIMENSIONAL INTEGRATED CIRCUIT STRUCTURE 有权

    公开(公告)号：US20240413136A1

    公开(公告)日：2024-12-12

    申请号：US18223539

    申请日：2023-07-18

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Tsung-Kai Yu ,  Chen-Hsiao Wang ,  Yi-Feng Hsu ,  Kai-Kuang Ho

    IPC: H01L25/10 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L23/522

    Abstract: The present invention provides a 3D integrated circuit structure formed by stacking semiconductor structures. The semiconductor structures form a multi-die heterogeneous 3D packaging by direct bonding the bonding pads of re-distribution layers. The same or different dies are used to produce the semiconductor structures through the back-end packaging process, and then hybrid bonding technology is used to stack and interconnect the semiconductor structures. The position of the bonding pad can be redefined by re-distribution layer, thereby overcoming the limitations of chip bonding pad position, chip size and quantity.

    WAFER WITH TEST STRUCTURE AND METHOD OF DICING WAFER
    8.
    发明申请
    WAFER WITH TEST STRUCTURE AND METHOD OF DICING WAFER 有权

    公开(公告)号：US20230018710A1

    公开(公告)日：2023-01-19

    申请号：US17386554

    申请日：2021-07-28

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Wei-Ren Huang ,  Chen-Hsiao Wang ,  Kai-Kuang Ho

    IPC: H01L21/78 ,  H01L21/311 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/66

    Abstract: A wafer with a test structure includes a wafer with a front side and a back side. A first die, a second die, a third die and a scribe line are disposed on the wafer. The scribe line is positioned between the dice. The first die includes a first dielectric layer and a first metal connection disposed within and on the first dielectric layer. A test structure and a dielectric layer are disposed on the scribe line, wherein the test structure is on the dielectric layer. Two first trenches are respectively disposed between the first dielectric layer and the dielectric layer and disposed at one side of the dielectric layer. Two second trenches penetrate the wafer, and each of the two second trenches respectively connects to a corresponding one of the two first trenches. A grinding tape covers the front side of the wafer and contacts the test structure.

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