-
公开(公告)号:US10340230B1
公开(公告)日:2019-07-02
申请号:US15847567
申请日:2017-12-19
Applicant: United Microelectronics Corp.
Inventor: Tsong-Lin Shen , Chen-Hsiao Wang , Sheng-Wei Hung , Chin-Tsai Chang , Hui-Lung Chou
IPC: H01L23/528 , H01L23/00 , H01L23/532
Abstract: A semiconductor chip is provided. The semiconductor chip includes at least one interlayer dielectric layer, a transmission pattern and a stress absorption structure. The at least one interlayer dielectric layer is disposed on a substrate. The transmission pattern is disposed on the at least one interlayer dielectric layer and within a peripheral region of the semiconductor chip. The transmission pattern is electrically connected to an external signal source. The stress absorption structure is disposed in the at least one interlayer dielectric layer within the peripheral region, and electrically connected to the transmission pattern. The stress absorption structure is covered by the transmission pattern.
-
公开(公告)号:US11774392B1
公开(公告)日:2023-10-03
申请号:US17701689
申请日:2022-03-23
Applicant: United Microelectronics Corp.
Inventor: Tsong-Lin Shen , Tsung-Yu Yang
CPC classification number: G01N27/24 , G01R31/2831
Abstract: A chip crack detection structure, including a substrate, a first chip crack detection ring, a second chip crack detection ring, and a seal ring, is provided. The first chip crack detection ring includes multiple first conductive layers stacked over the substrate and electrically connected to each other. A bottom surface of a lowermost conductive layer among the first conductive layers is not in contact with any plug. The second chip crack detection ring surrounds the first chip crack detection ring. The second chip crack detection ring includes multiple second conductive layers stacked over the substrate and electrically connected to each other. A bottom surface of a lowermost conductive layer among the second conductive layers is not in contact with any plug. The seal ring surrounds the second chip crack detection ring. The seal ring includes multiple third conductive layers stacked over the substrate and electrically connected to each other.
-
公开(公告)号:US20180162725A1
公开(公告)日:2018-06-14
申请号:US15373489
申请日:2016-12-09
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Tsong-Lin Shen , Chien-Chung Su , Chih-Cheng Wang , Yu-Chih Chuang , Sheng-Wei Hung , Min-Hung Wang , Chin-Tsai Chang
Abstract: A semiconductor device includes a semiconductor substrate comprising a MOS transistor. A MEMS device is integrally constructed above the MOS transistor. The MEMS device includes a bottom electrode in a second topmost metal layer, a diaphragm in a pad metal layer, and a cavity between the bottom electrode and the diaphragm.
-
公开(公告)号:US20230280298A1
公开(公告)日:2023-09-07
申请号:US17701689
申请日:2022-03-23
Applicant: United Microelectronics Corp.
Inventor: Tsong-Lin Shen , Tsung-Yu Yang
CPC classification number: G01N27/24 , G01R31/2831
Abstract: A chip crack detection structure, including a substrate, a first chip crack detection ring, a second chip crack detection ring, and a seal ring, is provided. The first chip crack detection ring includes multiple first conductive layers stacked over the substrate and electrically connected to each other. A bottom surface of a lowermost conductive layer among the first conductive layers is not in contact with any plug. The second chip crack detection ring surrounds the first chip crack detection ring. The second chip crack detection ring includes multiple second conductive layers stacked over the substrate and electrically connected to each other. A bottom surface of a lowermost conductive layer among the second conductive layers is not in contact with any plug. The seal ring surrounds the second chip crack detection ring. The seal ring includes multiple third conductive layers stacked over the substrate and electrically connected to each other.
-
5.
公开(公告)号:US10472232B2
公开(公告)日:2019-11-12
申请号:US15373489
申请日:2016-12-09
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Tsong-Lin Shen , Chien-Chung Su , Chih-Cheng Wang , Yu-Chih Chuang , Sheng-Wei Hung , Min-Hung Wang , Chin-Tsai Chang
Abstract: A semiconductor device includes a semiconductor substrate comprising a MOS transistor. A MEMS device is integrally constructed above the MOS transistor. The MEMS device includes a bottom electrode in a second topmost metal layer, a diaphragm in a pad metal layer, and a cavity between the bottom electrode and the diaphragm.
-
公开(公告)号:US20190189568A1
公开(公告)日:2019-06-20
申请号:US15847567
申请日:2017-12-19
Applicant: United Microelectronics Corp.
Inventor: Tsong-Lin Shen , Chen-Hsiao Wang , Sheng-Wei Hung , Chin-Tsai Chang , Hui-Lung Chou
IPC: H01L23/00 , H01L23/528 , H01L23/532
CPC classification number: H01L23/562 , H01L23/528 , H01L23/5329 , H01L24/05 , H01L24/13 , H01L2224/02381 , H01L2224/0401
Abstract: A semiconductor chip is provided. The semiconductor chip includes at least one interlayer dielectric layer, a transmission pattern and a stress absorption structure. The at least one interlayer dielectric layer is disposed on a substrate. The transmission pattern is disposed on the at least one interlayer dielectric layer and within a peripheral region of the semiconductor chip. The transmission pattern is electrically connected to an external signal source. The stress absorption structure is disposed in the at least one interlayer dielectric layer within the peripheral region, and electrically connected to the transmission pattern. The stress absorption structure is covered by the transmission pattern.
-
-
-
-
-