公开(公告)号：US20180047728A1

公开(公告)日：2018-02-15

申请号：US15723373

申请日：2017-10-03

Applicant: Texas Instruments Incorporated

Inventor： Kwan-Yong LIM ,  James Walter BLATCHFORD ,  Shashank S. EKBOTE ,  Younsung CHOI

IPC: H01L27/092 ,  H01L23/535 ,  H01L29/417 ,  H01L21/8234 ,  H01L21/8238

CPC classification number: H01L27/092 ,  H01L21/76897 ,  H01L21/823481 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L23/535 ,  H01L29/0847 ,  H01L29/4175 ,  H01L29/665 ,  H01L29/66636

Abstract: An integrated circuit with an MOS transistor abutting field oxide and a gate structure on the field oxide adjacent to the MOS transistor and a gap between an epitaxial source/drain and the field oxide is formed with a silicon dioxide-based gap filler in the gap. Metal silicide is formed on the exposed epitaxial source/drain region. A CESL is formed over the integrated circuit and a PMD layer is formed over the CESL. A contact is formed through the PMD layer and CESL to make an electrical connection to the metal silicide on the epitaxial source/drain region.

公开(公告)号：US20160322352A1

公开(公告)日：2016-11-03

申请号：US15204338

申请日：2016-07-07

Applicant: Texas Instruments Incorporated

Inventor： Himadri Sekhar PAL ,  Shashank S. EKBOTE ,  Youn Sung CHOI

IPC: H01L27/088 ,  H01L21/266 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/10 ,  H01L29/423 ,  H01L29/66 ,  H01L21/265 ,  H01L29/08

CPC classification number: H01L27/088 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/266 ,  H01L21/823418 ,  H01L21/823456 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/1095 ,  H01L29/167 ,  H01L29/42372 ,  H01L29/66537 ,  H01L29/6659 ,  H01L29/66659 ,  H01L29/7833 ,  H01L29/7835 ,  H01L29/7836

Abstract: An integrated circuit has two parallel digital transistors and a perpendicular analog transistor. The digital transistor gate lengths are within 10 percent of each other and the analog gate length is at least twice the digital transistor gate length. The first digital transistor and the analog transistor are implanted by a first LDD implant which includes a two sub-implant angled halo implant process with twist angles perpendicular to the first digital transistor gate edge and parallel to the analog transistor gate edge. The second digital transistor and the analog transistor are implanted by a second LDD implant which includes a two sub-implant angled halo implant process with twist angles perpendicular to the second digital transistor gate edge and parallel to the analog transistor gate edge. The first halo dose is at least 20 percent more than the second halo dose.

公开(公告)号：US20150270174A1

公开(公告)日：2015-09-24

申请号：US14726691

申请日：2015-06-01

Applicant: Texas Instruments Incorporated

Inventor： Himadri Sekhar PAL ,  Ebenezer ESHUN ,  Shashank S. EKBOTE

IPC: H01L21/8234 ,  H01L21/311 ,  H01L21/265 ,  H01L27/11

CPC classification number: H01L21/823425 ,  H01L21/26513 ,  H01L21/311 ,  H01L21/823412 ,  H01L27/0629 ,  H01L27/088 ,  H01L27/1104 ,  H01L27/1116 ,  H01L28/20 ,  H01L29/66477

Abstract: In an integrated circuit that includes an NMOS logic transistor, an NMOS SRAM transistor, and a resistor, the gate of the SRAM transistor is doped at the same time that the resistor is doped, thereby allowing the gate of the logic transistor to be separately doped without requiring any additional masking steps.

Abstract translation: 在包括NMOS逻辑晶体管，NMOS SRAM晶体管和电阻器的集成电路中，在掺杂电阻器的同时掺杂SRAM晶体管的栅极，从而允许逻辑晶体管的栅极被单独掺杂 而不需要任何额外的掩蔽步骤。

公开(公告)号：US20150170972A1

公开(公告)日：2015-06-18

申请号：US14563062

申请日：2014-12-08

Applicant: Texas Instruments Incorporated

Inventor： Kwan-Yong LIM ,  James Walter BLATCHFORD ,  Shashank S. EKBOTE ,  Younsung CHOI

IPC: H01L21/8234 ,  H01L27/092 ,  H01L21/8238

CPC classification number: H01L27/092 ,  H01L21/76897 ,  H01L21/823481 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L23/535 ,  H01L29/0847 ,  H01L29/4175 ,  H01L29/665 ,  H01L29/66636

Abstract: An integrated circuit with an MOS transistor abutting field oxide and a gate structure on the field oxide adjacent to the MOS transistor and a gap between an epitaxial source/drain and the field oxide is formed with a silicon dioxide-based gap filler in the gap. Metal silicide is formed on the exposed epitaxial source/drain region. A CESL is formed over the integrated circuit and a PMD layer is formed over the CESL. A contact is formed through the PMD layer and CESL to make an electrical connection to the metal silicide on the epitaxial source/drain region.

Abstract translation: 在MOS间隔填充有二氧化硅的间隙填料，形成与MOS晶体管邻接的MOS晶体管和与MOS晶体管相邻的场氧化物上的栅极结构和外延源极/漏极与场氧化物之间的间隙的集成电路。 在暴露的外延源极/漏极区上形成金属硅化物。 在集成电路上形成CESL，并且在CESL上形成PMD层。 通过PMD层和CESL形成接触以与外延源极/漏极区上的金属硅化物形成电连接。

公开(公告)号：US20170047329A1

公开(公告)日：2017-02-16

申请号：US15336248

申请日：2016-10-27

Applicant: Texas Instruments Incorporated

Inventor： Kwan-Yong LIM ,  James Walter BLATCHFORD ,  Shashank S. EKBOTE ,  Younsung CHOI

IPC: H01L27/092 ,  H01L21/8238 ,  H01L21/8234 ,  H01L29/417 ,  H01L23/535

CPC classification number: H01L27/092 ,  H01L21/76897 ,  H01L21/823481 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L23/535 ,  H01L29/0847 ,  H01L29/4175 ,  H01L29/665 ,  H01L29/66636

Abstract: An integrated circuit with an MOS transistor abutting field oxide and a gate structure on the field oxide adjacent to the MOS transistor and a gap between an epitaxial source/drain and the field oxide is formed with a silicon dioxide-based gap filler in the gap. Metal silicide is formed on the exposed epitaxial source/drain region. A CESL is formed over the integrated circuit and a PMD layer is formed over the CESL. A contact is formed through the PMD layer and CESL to make an electrical connection to the metal silicide on the epitaxial source/drain region.

Abstract translation: 在MOS间隔填充有二氧化硅的间隙填料，形成与MOS晶体管邻接的MOS晶体管和与MOS晶体管相邻的场氧化物上的栅极结构和外延源极/漏极与场氧化物之间的间隙的集成电路。 在暴露的外延源极/漏极区上形成金属硅化物。 在集成电路上形成CESL，并且在CESL上形成PMD层。 通过PMD层和CESL形成接触以与外延源极/漏极区上的金属硅化物形成电连接。

公开(公告)号：US20160043076A1

公开(公告)日：2016-02-11

申请号：US14920310

申请日：2015-10-22

Applicant: Texas Instruments Incorporated

Inventor： Himadri Sekhar PAL ,  Shashank S. EKBOTE ,  Youn Sung CHOI

IPC: H01L27/088 ,  H01L29/78 ,  H01L29/10 ,  H01L29/08

CPC classification number: H01L27/088 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/266 ,  H01L21/823418 ,  H01L21/823456 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/1095 ,  H01L29/167 ,  H01L29/42372 ,  H01L29/66537 ,  H01L29/6659 ,  H01L29/66659 ,  H01L29/7833 ,  H01L29/7835 ,  H01L29/7836

Abstract: An integrated circuit has two parallel digital transistors and a perpendicular analog transistor. The digital transistor gate lengths are within 10 percent of each other and the analog gate length is at least twice the digital transistor gate length. The first digital transistor and the analog transistor are implanted by a first LDD implant which includes a two sub-implant angled halo implant process with twist angles perpendicular to the first digital transistor gate edge and parallel to the analog transistor gate edge. The second digital transistor and the analog transistor are implanted by a second LDD implant which includes a two sub-implant angled halo implant process with twist angles perpendicular to the second digital transistor gate edge and parallel to the analog transistor gate edge. The first halo dose is at least 20 percent more than the second halo dose.

公开(公告)号：US20160027888A1

公开(公告)日：2016-01-28

申请号：US14875343

申请日：2015-10-05

Applicant: Texas Instruments Incorporated

Inventor： Shashank S. EKBOTE ,  Kwan-Yong LIM ,  Ebenezer ESHUN ,  Youn Sung CHOI

IPC: H01L29/45 ,  H01L29/78 ,  H01L29/417 ,  H01L27/02 ,  H01L29/08 ,  H01L27/088 ,  H01L29/161

CPC classification number: H01L29/45 ,  H01L21/28123 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823443 ,  H01L27/0207 ,  H01L27/088 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/41725 ,  H01L29/458 ,  H01L29/665 ,  H01L29/66636 ,  H01L29/7848

Abstract: An integrated circuit includes a PMOS gate structure and a gate structure on adjacent field oxide. An epitaxy hard mask is formed over the gate structure on the field oxide so that the epitaxy hard mask overlaps the semiconductor material in PMOS source/drain region. SiGe semiconductor material is epitaxially formed in the source/drain regions, so that that a top edge of the SiGe semiconductor material at the field oxide does not extend more than one third of a depth of the SiGe in the source/drain region abutting the field oxide. Dielectric spacers on lateral surfaces of the gate structure on the field oxide extend onto the SiGe; at least one third of the SiGe is exposed. Metal silicide covers at least one third of a top surface of the SiGe. A contact has at least half of a bottom of the contact directly contacts the metal silicide on the SiGe.

公开(公告)号：US20150287801A1

公开(公告)日：2015-10-08

申请号：US14744384

申请日：2015-06-19

Applicant: Texas Instruments Incorporated

Inventor： Shashank S. EKBOTE ,  Kwan-Yong LIM ,  Ebenezer ESHUN ,  Youn Sung CHOI

IPC: H01L29/45 ,  H01L27/02 ,  H01L27/088 ,  H01L29/08 ,  H01L29/161

CPC classification number: H01L29/45 ,  H01L21/28123 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823443 ,  H01L27/0207 ,  H01L27/088 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/41725 ,  H01L29/458 ,  H01L29/665 ,  H01L29/66636 ,  H01L29/7848

Abstract: An integrated circuit includes a PMOS gate structure and a gate structure on adjacent field oxide. An epitaxy hard mask is formed over the gate structure on the field oxide so that the epitaxy hard mask overlaps the semiconductor material in PMOS source/drain region. SiGe semiconductor material is epitaxially formed in the source/drain regions, so that that a top edge of the SiGe semiconductor material at the field oxide does not extend more than one third of a depth of the SiGe in the source/drain region abutting the field oxide. Dielectric spacers on lateral surfaces of the gate structure on the field oxide extend onto the SiGe; at least one third of the SiGe is exposed. Metal silicide covers at least one third of a top surface of the SiGe. A contact has at least half of a bottom of the contact directly contacts the metal silicide on the SiGe.

Abstract translation: 集成电路包括PMOS栅极结构和相邻场氧化物上的栅极结构。 在场氧化物上的栅极结构上形成外延硬掩模，使得外延硬掩模与PMOS源极/漏极区域中的半导体材料重叠。 SiGe半导体材料在源极/漏极区域中外延形成，使得在场氧化物处的SiGe半导体材料的顶部边缘不超过邻接该场的源极/漏极区域中的SiGe的深度的三分之一以上 氧化物。 场氧化物上的栅极结构的侧表面上的介电隔离物延伸到SiGe上; 至少有三分之一的SiGe被暴露。 金属硅化物覆盖SiGe的顶表面的至少三分之一。 触点具有触点底部的至少一半直接接触SiGe上的金属硅化物。

公开(公告)号：US20150287717A1

公开(公告)日：2015-10-08

申请号：US14244180

申请日：2014-04-03

Applicant: Texas Instruments Incorporated

Inventor： Himadri Sekhar PAL ,  Shashank S. EKBOTE ,  Youn Sung CHOI

IPC: H01L27/088 ,  H01L29/66 ,  H01L29/10 ,  H01L21/8234 ,  H01L29/423 ,  H01L21/265 ,  H01L21/266 ,  H01L29/167 ,  H01L29/78 ,  H01L29/08

CPC classification number: H01L27/088 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/266 ,  H01L21/823418 ,  H01L21/823456 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/1095 ,  H01L29/167 ,  H01L29/42372 ,  H01L29/66537 ,  H01L29/6659 ,  H01L29/66659 ,  H01L29/7833 ,  H01L29/7835 ,  H01L29/7836

Abstract: An integrated circuit has two parallel digital transistors and a perpendicular analog transistor. The digital transistor gate lengths are within 10 percent of each other and the analog gate length is at least twice the digital transistor gate length. The first digital transistor and the analog transistor are implanted by a first LDD implant which includes a two sub-implant angled halo implant process with twist angles perpendicular to the first digital transistor gate edge and parallel to the analog transistor gate edge. The second digital transistor and the analog transistor are implanted by a second LDD implant which includes a two sub-implant angled halo implant process with twist angles perpendicular to the second digital transistor gate edge and parallel to the analog transistor gate edge. The first halo dose is at least 20 percent more than the second halo dose.

Abstract translation: 集成电路具有两个并联数字晶体管和垂直模拟晶体管。 数字晶体管栅极长度在彼此的10％以内，并且模拟栅极长度至少是数字晶体管栅极长度的两倍。 第一数字晶体管和模拟晶体管通过第一LDD注入来注入，该LDD注入包括具有垂直于第一数字晶体管栅极边缘并且平行于模拟晶体管栅极边缘的扭转角的两个子注入角成角度的注入工艺。 第二数字晶体管和模拟晶体管通过第二LDD注入来注入，该LDD注入包括具有垂直于第二数字晶体管栅极边缘并且平行于模拟晶体管栅极边缘的扭转角的两个子注入成角度的晕圈注入工艺。 第一个光晕剂量比第二个晕轮剂量多至少20％。

公开(公告)号：US20150054084A1

公开(公告)日：2015-02-26

申请号：US13972973

申请日：2013-08-22

Applicant: Texas Instruments Incorporated

Inventor： Shashank S. EKBOTE ,  Kwan-Yong LIM ,  Ebenezer ESHUN ,  Youn Sung CHOI

IPC: H01L27/088 ,  H01L29/66

CPC classification number: H01L29/45 ,  H01L21/28123 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823443 ,  H01L27/0207 ,  H01L27/088 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/41725 ,  H01L29/458 ,  H01L29/665 ,  H01L29/66636 ,  H01L29/7848

Abstract: An integrated circuit includes a PMOS gate structure and a gate structure on adjacent field oxide. An epitaxy hard mask is formed over the gate structure on the field oxide so that the epitaxy hard mask overlaps the semiconductor material in PMOS source/drain region. SiGe semiconductor material is epitaxially formed in the source/drain regions, so that that a top edge of the SiGe semiconductor material at the field oxide does not extend more than one third of a depth of the SiGe in the source/drain region abutting the field oxide. Dielectric spacers on lateral surfaces of the gate structure on the field oxide extend onto the SiGe; at least one third of the SiGe is exposed. Metal silicide covers at least one third of a top surface of the SiGe. A contact has at least half of a bottom of the contact directly contacts the metal silicide on the SiGe.

Abstract translation: 集成电路包括PMOS栅极结构和相邻场氧化物上的栅极结构。 在场氧化物上的栅极结构上形成外延硬掩模，使得外延硬掩模与PMOS源极/漏极区域中的半导体材料重叠。 SiGe半导体材料在源极/漏极区域中外延形成，使得在场氧化物处的SiGe半导体材料的顶部边缘不超过邻接该场的源极/漏极区域中的SiGe的深度的三分之一以上 氧化物。 场氧化物上的栅极结构的侧表面上的介电隔离物延伸到SiGe上; 至少有三分之一的SiGe被暴露。 金属硅化物覆盖SiGe的顶表面的至少三分之一。 触点具有触点底部的至少一半直接接触SiGe上的金属硅化物。