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公开(公告)号：US20240363469A1
公开(公告)日：2024-10-31
申请号：US18765696
申请日：2024-07-08
IPC分类号： H01L23/31 , H01L21/56 , H01L21/768 , H01L23/48 , H01L23/528 , H01L25/065
CPC分类号： H01L23/3185 , H01L21/56 , H01L21/76829 , H01L23/481 , H01L23/5283 , H01L25/0657
摘要： The present disclosure, in some embodiments, relates to an integrated chip structure. The integrated chip structure includes a substrate and an interconnect structure on the substrate. The interconnect structure has a plurality of interconnects disposed within a dielectric structure. A dielectric material is along a sidewall of the interconnect structure. The dielectric material extends to within cracks in the sidewall of the dielectric structure.
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公开(公告)号：US12062687B2
公开(公告)日：2024-08-13
申请号：US18215707
申请日：2023-06-28
发明人： Hong-Yang Chen , Tian Sheng Lin , Yi-Cheng Chiu , Hung-Chou Lin , Yi-Min Chen , Kuo-Ming Wu , Chiu-Hua Chung
IPC分类号： H01L27/108 , H01L27/01 , H01L27/06 , H01L29/76 , H01L31/119 , H01L49/02
CPC分类号： H01L28/60 , H01L27/01 , H01L27/0629
摘要： A capacitor structure for a power semiconductor device includes a semiconductor substrate, an isolation insulating layer having a ring-shape and including an outer periphery and an inner periphery defining an opening region, a first electrode disposed on the isolation insulating layer, a dielectric layer disposed on the first electrode, and a second electrode disposed on the dielectric layer.
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公开(公告)号：US20240198455A1
公开(公告)日：2024-06-20
申请号：US18589527
申请日：2024-02-28
发明人： Kuo-Ming Wu , Yung-Lung Lin , Hau-Yi Hsiao , Sheng-Chau Chen , Cheng-Yuan Tsai
IPC分类号： B23K26/361 , B23K26/035 , B23K26/062 , H01L21/02 , H01L21/66
CPC分类号： B23K26/361 , B23K26/035 , B23K26/062 , H01L21/02021 , H01L22/10
摘要： In some embodiments, the present disclosure relates to a method of trimming an annular portion of a wafer. The method includes aligning the wafer over a wafer chuck. The method uses a rotating blade having a first rotational speed to remove the annular portion from an upper surface of the wafer. While the rotating blade is removing the annular portion of the upper surface of the wafer, measuring a parameter of the wafer at a position adjacent to the rotating blade. Lastly, the method involves changing the first rotation speed of the rotating blade to a second rotational speed when the parameter is greater than a predetermined threshold.
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公开(公告)号：US20240079268A1
公开(公告)日：2024-03-07
申请号：US18506186
申请日：2023-11-10
IPC分类号： H01L21/768 , H01L23/00 , H01L23/48 , H01L23/522 , H01L23/528 , H01L25/00 , H01L25/065
CPC分类号： H01L21/76834 , H01L21/76822 , H01L23/481 , H01L23/5226 , H01L23/528 , H01L24/80 , H01L25/0657 , H01L25/50 , H01L2224/80986
摘要： The present disclosure, in some embodiments, relates to a method of forming an integrated chip structure. The method may be performed by forming a plurality of interconnect layers within a first interconnect structure disposed over an upper surface of a first semiconductor substrate. An edge trimming process is performed to remove parts of the first interconnect structure and the first semiconductor substrate along a perimeter of the first semiconductor substrate. The edge trimming process results in the first semiconductor substrate having a recessed surface coupled to the upper surface by way of an interior sidewall disposed directly over the first semiconductor substrate. A dielectric capping structure is formed onto a sidewall of the first interconnect structure after performing the edge trimming process.
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公开(公告)号：US11842992B2
公开(公告)日：2023-12-12
申请号：US17748511
申请日：2022-05-19
发明人： Kuo-Ming Wu , Kuan-Liang Liu , Wen-De Wang , Yung-Lung Lin
CPC分类号： H01L25/50 , H01L23/585 , H01L24/29 , H01L24/66 , H01L24/69 , H01L24/83 , H01L24/89 , H01L23/3114 , H01L23/564 , H01L24/73 , H01L24/81 , H01L25/0657 , H01L25/18 , H01L2224/1145 , H01L2224/1161 , H01L2224/1162 , H01L2224/11462 , H01L2224/11845 , H01L2224/13147 , H01L2224/17517 , H01L2224/2745 , H01L2224/2761 , H01L2224/2762 , H01L2224/27462 , H01L2224/27845 , H01L2224/29011 , H01L2224/29012 , H01L2224/29015 , H01L2224/29019 , H01L2224/29035 , H01L2224/29147 , H01L2224/73103 , H01L2224/73203 , H01L2224/81193 , H01L2224/81815 , H01L2224/81895 , H01L2224/8392 , H01L2224/83193 , H01L2224/83815 , H01L2224/83895 , H01L2224/83935 , H01L2224/83951 , H01L2224/13147 , H01L2924/00014 , H01L2224/29147 , H01L2924/00014 , H01L2224/27462 , H01L2924/00014 , H01L2224/2745 , H01L2924/00014 , H01L2224/11462 , H01L2924/00014 , H01L2224/1145 , H01L2924/00014 , H01L2224/1161 , H01L2924/00014 , H01L2224/1162 , H01L2924/00014 , H01L2224/2761 , H01L2924/00014 , H01L2224/2762 , H01L2924/00014 , H01L2224/83815 , H01L2924/00014 , H01L2224/81895 , H01L2924/00014 , H01L2224/81815 , H01L2924/00014 , H01L2224/83935 , H01L2924/00012 , H01L2224/29012 , H01L2924/00012
摘要： Some embodiments relate to a three-dimensional (3D) integrated circuit (IC). The 3D IC includes a first IC die comprising a first semiconductor substrate, and a first interconnect structure over the first semiconductor substrate. The 3D IC also includes a second IC die comprising a second semiconductor substrate, and a second interconnect structure that separates the second semiconductor substrate from the first interconnect structure. A seal ring structure separates the first interconnect structure from the second interconnect structure and perimetrically surrounds a gas reservoir between the first IC die and second IC die. The seal ring structure includes a sidewall gas-vent opening structure configured to allow gas to pass between the gas reservoir and an ambient environment surrounding the 3D IC.
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公开(公告)号：US11728374B2
公开(公告)日：2023-08-15
申请号：US17498561
申请日：2021-10-11
发明人： Hong-Yang Chen , Tian Sheng Lin , Yi-Cheng Chiu , Hung-Chou Lin , Yi-Min Chen , Kuo-Ming Wu , Chiu-Hua Chung
IPC分类号： H01L27/108 , H01L29/76 , H01L31/119 , H01L49/02 , H01L27/01 , H01L27/06
CPC分类号： H01L28/60 , H01L27/01 , H01L27/0629
摘要： A capacitor structure for a power semiconductor device includes a semiconductor substrate, an isolation insulating layer having a ring-shape and including an outer periphery and an inner periphery defining an opening region, a first electrode disposed on the isolation insulating layer, a dielectric layer disposed on the first electrode, and a second electrode disposed on the dielectric layer.
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公开(公告)号：US11721758B2
公开(公告)日：2023-08-08
申请号：US17103611
申请日：2020-11-24
发明人： Jia-Rui Lee , Kuo-Ming Wu , Yi-Chun Lin
IPC分类号： H01L29/78 , H01L21/762 , H01L29/06 , H01L29/423 , H01L21/76 , H01L29/66
CPC分类号： H01L29/7825 , H01L21/76 , H01L21/762 , H01L29/0653 , H01L29/42368 , H01L29/42376 , H01L29/66704 , H01L29/7835
摘要： A semiconductor structure is disclosed. The semiconductor structure includes: a substrate; an isolation region adjacent to the drain region; a gate electrode over the substrate and further downwardly extends into the substrate, wherein a portion of the gate electrode below a top surface of the substrate abuts the isolation region; and a source region and a drain region formed in the substrate on either side of the gate structure. An associated method for fabricating the semiconductor structure is also disclosed.
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公开(公告)号：US20220262770A1
公开(公告)日：2022-08-18
申请号：US17729286
申请日：2022-04-26
发明人： Kuo-Ming Wu , Ching-Chun Wang , Dun-Nian Yaung , Hsing-Chih Lin , Jen-Cheng Liu , Min-Feng Kao , Yung-Lung Lin , Shih-Han Huang , I-Nan Chen
IPC分类号： H01L25/065 , H01L23/528 , H01L23/48 , H01L25/00 , H01L23/00 , H01L23/532
摘要： A three-dimensional (3D) integrated circuit (IC) is provided. In some embodiments, the 3D IC comprises a first IC die comprising a first substrate, a first interconnect structure disposed over the first substrate, and a first through substrate via(TSV) disposed through the first substrate. The 3D IC further comprises a second IC die comprising a second substrate, a second interconnect structure disposed over the second substrate, and a second TSV disposed through the second substrate. The 3D IC further comprises a bonding structure arranged between back sides of the first IC die and the second IC die opposite to corresponding interconnect structures and bonding the first IC die and the second IC die. The bonding structure comprises conductive features disposed between and electrically connecting the first TSV and the second TSV.
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公开(公告)号：US11189613B2
公开(公告)日：2021-11-30
申请号：US16709323
申请日：2019-12-10
发明人： Jia-Rui Lee , Kuo-Ming Wu , Yi-Chun Lin , Alexander Kalnitsky
IPC分类号： H01L27/088 , H01L29/06 , H01L29/08 , H01L21/8234 , H01L21/762 , H01L29/66 , H01L29/78 , H01L29/423
摘要： A semiconductor device and a method of forming the same are provided. The semiconductor device includes a transistor and a diode. The transistor includes a first gate region electrically coupled to a gate driver, and a first source region and a first drain region on two sides of the first gate region. The diode includes two terminals coupled between the first drain region of the transistor and a reference voltage. The transistor has a threshold voltage greater than that of the diode.
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公开(公告)号：US20180033888A1
公开(公告)日：2018-02-01
申请号：US15728740
申请日：2017-10-10
发明人： Po-Yu Chen , Wan-Hua Huang , Jing-Ying Chen , Kuo-Ming Wu
CPC分类号： H01L29/7835 , H01L29/0653 , H01L29/1087 , H01L29/456 , H01L29/4933 , H01L29/665 , H01L29/66659 , H01L29/66681
摘要： A device comprises a buried layer over a substrate, a first well over the buried layer, a first high voltage region and a second high voltage region extending through the first well, a first drain/source region in the first high voltage region, a first gate electrode over the first well, a first spacer on a first side of the first gate electrode, wherein the first spacer is between the first drain/source region and the first gate electrode, a second spacer on a second side of the first gate electrode, a second drain/source region in the second high voltage region and a first isolation region in the second high voltage region and between the second drain/source region and the first gate electrode.
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