公开(公告)号：US20200044060A1

公开(公告)日：2020-02-06

申请号：US16396405

申请日：2019-04-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chao-Ching CHENG ,  Hung-Li CHIANG ,  Tzu-Chiang CHEN ,  I-Sheng CHEN

IPC: H01L29/66 ,  H01L29/08 ,  H01L21/311 ,  H01L21/02 ,  H01L29/165 ,  H01L29/06 ,  H01L27/088 ,  H01L29/423

Abstract: In a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed over a bottom fin structure. A sacrificial gate structure having sidewall spacers is formed over the fin structure. A source/drain region of the fin structure, which is not covered by the sacrificial gate structure, is removed. The second semiconductor layers are laterally recessed. Dielectric inner spacers are formed on lateral ends of the recessed second semiconductor layers. The first semiconductor layers are laterally recessed. A source/drain epitaxial layer is formed to contact lateral ends of the recessed first semiconductor layer. The second semiconductor layers are removed thereby releasing the first semiconductor layers in a channel region. A gate structure is formed around the first semiconductor layers.

公开(公告)号：US20200006155A1

公开(公告)日：2020-01-02

申请号：US16281679

申请日：2019-02-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hung-Li CHIANG ,  Chih-Liang CHEN ,  Tzu-Chiang CHEN ,  I-Sheng CHEN ,  Lei-Chun CHOU

IPC: H01L21/8238 ,  H01L29/06 ,  H01L29/78 ,  H01L27/092 ,  H01L29/66

Abstract: A method of manufacturing a semiconductor device includes forming a plurality of fin structures extending in a first direction over a semiconductor substrate. Each fin structure includes a first region proximate to the semiconductor substrate and a second region distal to the semiconductor substrate. An electrically conductive layer is formed between the first regions of a first adjacent pair of fin structures. A gate electrode structure is formed extending in a second direction substantially perpendicular to the first direction over the fin structure second region, and a metallization layer including at least one conductive line is formed over the gate electrode structure.

公开(公告)号：US20180175214A1

公开(公告)日：2018-06-21

申请号：US15719121

申请日：2017-09-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： I-Sheng CHEN ,  Szu-Wei HUANG ,  Hung-Li CHIANG ,  Cheng-Hsien WU ,  Chih Chieh YEH

IPC: H01L29/786 ,  H01L29/66 ,  H01L29/423 ,  H01L29/78 ,  H01L29/06 ,  H01L29/10

CPC classification number: H01L29/78696 ,  B82Y10/00 ,  H01L21/823807 ,  H01L27/04 ,  H01L29/045 ,  H01L29/0657 ,  H01L29/0673 ,  H01L29/1033 ,  H01L29/401 ,  H01L29/42364 ,  H01L29/42372 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66757 ,  H01L29/775 ,  H01L29/7827

Abstract: A semiconductor device includes channel layers disposed over a substrate, a source/drain region disposed over the substrate, a gate dielectric layer disposed on and wrapping each of the channel layers, and a gate electrode layer disposed on the gate dielectric layer and wrapping each of the channel layers. Each of the channel layers includes a semiconductor wire made of a core region, and one or more shell regions. The core region has an approximately square-shape cross section and a first shell of the one or more shells forms a first shell region of an approximately rhombus-shape cross section around the core region and is connected to an adjacent first shell region corresponding to a neighboring semiconductor wire.

公开(公告)号：US20180151717A1

公开(公告)日：2018-05-31

申请号：US15429861

申请日：2017-02-10

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chao-Ching CHENG ,  Chih Chieh YEH ,  Cheng-Hsien WU ,  Hung-Li CHIANG ,  Jung-Piao CHIU ,  Tzu-Chiang CHEN ,  Tsung-Lin LEE ,  Yu-Lin YANG ,  I-Sheng CHEN

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/165 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7845

Abstract: A semiconductor device includes a fin field effect transistor (FinFET). The FinFET includes a channel disposed on a fin, a gate disposed over the channel and a source and drain. The channel includes at least two pairs of a first semiconductor layer and a second semiconductor layer formed on the first semiconductor layer. The first semiconductor layer has a different lattice constant than the second semiconductor layer. A thickness of the first semiconductor layer is three to ten times a thickness of the second semiconductor layer at least in one pair.

公开(公告)号：US20210375693A1

公开(公告)日：2021-12-02

申请号：US17225249

申请日：2021-04-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： I-Sheng CHEN ,  Yi-Jing LI ,  Chen-Heng LI

IPC: H01L21/8234 ,  H01L27/088 ,  H01L21/762

Abstract: The present disclosure describes a method that includes forming a fin protruding from a substrate, the fin including a first sidewall and a second sidewall formed opposite to the first sidewall. The method also includes depositing a shallow-trench isolation (STI) material on the substrate. Depositing the STI material includes depositing a first portion of the STI material in contact with the first sidewall and depositing a second portion of the STI material in contact with the second sidewall. The method also includes performing a first etching process on the STI material to etch the first portion of the STI material at a first etching rate and the second portion of the STI material at a second etching rate greater than the first etching rate. The method also includes performing a second etching process on the STI material to etch the first portion of the STI material at a third etching rate and the second portion of the STI material at a fourth etching rate less than the third etching rate.

公开(公告)号：US20210159124A1

公开(公告)日：2021-05-27

申请号：US17141117

申请日：2021-01-04

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chao-Ching CHENG ,  I-Sheng CHEN ,  Hung-Li CHIANG ,  Tzu-Chiang CHEN

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66 ,  H01L21/02 ,  H01L21/311

Abstract: In a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers containing Ge and second semiconductor layers are alternately stacked, is formed over a bottom fin structure. A Ge concentration in the first semiconductor layers is increased. A sacrificial gate structure is formed over the fin structure. A source/drain epitaxial layer is formed over a source/drain region of the fin structure. The sacrificial gate structure is removed. The second semiconductor layers in a channel region are removed, thereby releasing the first semiconductor layers in which the Ge concentration is increased. A gate structure is formed around the first semiconductor layers in which the Ge concentration is increased.

公开(公告)号：US20200013904A1

公开(公告)日：2020-01-09

申请号：US16574318

申请日：2019-09-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wilman TSAI ,  Cheng-Hsien WU ,  I-Sheng CHEN ,  Stefan RUSU

IPC: H01L29/786 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L27/092

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a substrate including a first fin portion, a first nanostructure over the first fin portion. The first nanostructure has a dumbbell shape. The first nanostructure includes a semiconductor material layer over the first fin portion, and a cladding layer surrounding the semiconductor material layer. The semiconductor material layer has a rectangular shape, and the cladding layer has a hexagonal or quadrilateral shape. The semiconductor device structure includes a first gate structure surrounding the first nanostructure.

公开(公告)号：US20190172939A1

公开(公告)日：2019-06-06

申请号：US16207067

申请日：2018-11-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： I-Sheng CHEN ,  Chih Chieh YEH ,  Cheng-Hsien WU

IPC: H01L29/78 ,  H01L27/092 ,  H01L29/66 ,  H01L29/10 ,  H01L29/786 ,  H01L29/417 ,  H01L21/8238 ,  H01L29/423 ,  H01L29/45

CPC classification number: H01L29/785 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/1054 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/456 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7851 ,  H01L29/7853 ,  H01L29/78696 ,  H01L2029/7858

Abstract: A semiconductor device includes first channel layers disposed over a substrate, a first source/drain region disposed over the substrate, a gate dielectric layer disposed on each of the first channel layers, a gate electrode layer disposed on the gate dielectric. Each of the first channel layers includes a semiconductor wire made of a first semiconductor material. The semiconductor wire passes through the first source/drain region and enters into an anchor region. At the anchor region, the semiconductor wire has no gate electrode layer and no gate dielectric, and is sandwiched by a second semiconductor material.

公开(公告)号：US20190088797A1

公开(公告)日：2019-03-21

申请号：US16196329

申请日：2018-11-20

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： I-Sheng CHEN ,  Szu-Wei HUANG ,  Hung-Li CHIANG ,  Cheng-Hsien WU ,  Chih Chieh YEH

IPC: H01L29/786 ,  H01L29/78 ,  H01L29/66 ,  H01L29/423 ,  H01L29/06 ,  H01L29/04 ,  H01L27/04 ,  H01L29/775 ,  H01L29/40 ,  B82Y10/00 ,  H01L29/10

Abstract: A semiconductor device includes channel layers disposed over a substrate, a source/drain region disposed over the substrate, a gate dielectric layer disposed on and wrapping each of the channel layers, and a gate electrode layer disposed on the gate dielectric layer and wrapping each of the channel layers. Each of the channel layers includes a semiconductor wire made of a core region, and one or more shell regions. The core region has an approximately square-shape cross section and a first shell of the one or more shells forms a first shell region of an approximately rhombus-shape cross section around the core region and is connected to an adjacent first shell region corresponding to a neighboring semiconductor wire.

公开(公告)号：US20190067125A1

公开(公告)日：2019-02-28

申请号：US15885359

申请日：2018-01-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hung-Li CHIANG ,  Chao-Ching CHENG ,  Chih-Liang CHEN ,  Tzu-Chiang CHEN ,  Ta-Pen GUO ,  Yu-Lin YANG ,  I-Sheng CHEN ,  Szu-Wei HUANG

IPC: H01L21/8238 ,  H01L27/092 ,  H01L27/11 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L29/66

CPC classification number: H01L21/823814 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/092 ,  H01L27/0924 ,  H01L27/1104 ,  H01L27/1108 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/78618 ,  H01L29/78696

Abstract: In a method, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. A sacrificial gate structure is formed over the fin structure. The first semiconductor layers are etched at a source/drain region of the fin structure, which is not covered by the sacrificial gate structure, thereby forming a first source/drain space in which the second semiconductor layers are exposed. A dielectric layer is formed at the first source/drain space, thereby covering the exposed second semiconductor layers. The dielectric layer and part of the second semiconductor layers are etched, thereby forming a second source/drain space. A source/drain epitaxial layer is formed in the second source/drain space. At least one of the second semiconductor layers is in contact with the source/drain epitaxial layer, and at least one of the second semiconductor layers is separated from the source/drain epitaxial layer.