公开(公告)号：US20230009485A1

公开(公告)日：2023-01-12

申请号：US17651869

申请日：2022-02-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Weng Chang ,  Hsiang-Pi Chang ,  Huang-Lin Chao ,  Chung-Liang Cheng ,  Chi On Chui ,  Kun-Yu Lee ,  Tzer-Min Shen ,  Yen-Tien Tung ,  Chun-I Wu

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/324

Abstract: A method includes removing a first dummy gate stack and a second dummy gate stack to form a first trench and a second trench. The first dummy gate stack and the second dummy gate stack are in a first device region and a second device region, respectively. The method further includes depositing a first gate dielectric layer and a second gate dielectric layer extending into the first trench and the second trench, respectively, forming a fluorine-containing layer comprising a first portion over the first gate dielectric layer, and a second portion over the second gate dielectric layer, removing the second portion, performing an annealing process to diffuse fluorine in the first portion into the first gate dielectric layer, and at a time after the annealing process, forming a first work-function layer and a second work-function layer over the first gate dielectric layer and the second gate dielectric layer, respectively.

公开(公告)号：US20250063778A1

公开(公告)日：2025-02-20

申请号：US18934076

申请日：2024-10-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Weng Chang ,  Hsiang-Pi Chang ,  Huang-Lin Chao ,  Chung-Liang Cheng ,  Chi On Chui ,  Kun-Yu Lee ,  Tzer-Min Shen ,  Yen-Tien Tung ,  Chun-I Wu

IPC: H01L29/06 ,  H01L21/324 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

Abstract: A method includes removing a first dummy gate stack and a second dummy gate stack to form a first trench and a second trench. The first dummy gate stack and the second dummy gate stack are in a first device region and a second device region, respectively. The method further includes depositing a first gate dielectric layer and a second gate dielectric layer extending into the first trench and the second trench, respectively, forming a fluorine-containing layer comprising a first portion over the first gate dielectric layer, and a second portion over the second gate dielectric layer, removing the second portion, performing an annealing process to diffuse fluorine in the first portion into the first gate dielectric layer, and at a time after the annealing process, forming a first work-function layer and a second work-function layer over the first gate dielectric layer and the second gate dielectric layer, respectively.

公开(公告)号：US11908702B2

公开(公告)日：2024-02-20

申请号：US17406874

申请日：2021-08-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsiang-Pi Chang ,  Chung-Liang Cheng ,  I-Ming Chang ,  Yao-Sheng Huang ,  Huang-Lin Chao

IPC: H01L21/3115 ,  H01L29/66 ,  H01L29/78 ,  H01L21/477 ,  H01L21/02 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/51 ,  H01L27/092

CPC classification number: H01L21/3115 ,  H01L21/02192 ,  H01L21/477 ,  H01L21/823431 ,  H01L21/823857 ,  H01L27/0924 ,  H01L29/517 ,  H01L29/66795 ,  H01L29/7851

Abstract: A semiconductor device with different configurations of gate structures and a method of fabricating the same are disclosed. The method includes forming a fin structure on a substrate, forming a gate opening on the fin structure, forming a metallic oxide layer within the gate opening, forming a first dielectric layer on the metallic oxide layer, forming a second dielectric layer on the first dielectric layer, forming a work function metal (WFM) layer on the second dielectric layer, and forming a gate metal fill layer on the WFM layer. The forming the first dielectric layer includes depositing an oxide material with an oxygen areal density less than an oxygen areal density of the metallic oxide layer.

公开(公告)号：US10985265B2

公开(公告)日：2021-04-20

申请号：US16548446

申请日：2019-08-22

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chung-Liang Cheng ,  I-Ming Chang ,  Hsiang-Pi Chang ,  Hsueh-Wen Tsau ,  Ziwei Fang ,  Huang-Lin Chao

IPC: H01L29/66 ,  H01L29/78

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a semiconductor layer on a semiconductor substrate, forming an interfacial layer on the semiconductor layer, forming a first gate dielectric layer on the interfacial layer, introducing fluorine on the first gate dielectric layer, annealing the first gate dielectric layer, forming a second gate dielectric layer on the first gate dielectric layer, introducing fluorine on the second gate dielectric layer, annealing the second gate dielectric layer, and forming a gate stack structure on the second gate dielectric layer.

公开(公告)号：US10971402B2

公开(公告)日：2021-04-06

申请号：US16443016

申请日：2019-06-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Liang Cheng ,  I-Ming Chang ,  Hsiang-Pi Chang ,  Yu-Wei Lu ,  Ziwei Fang ,  Huang-Lin Chao

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/10 ,  H01L21/02

Abstract: A method includes providing a channel region and growing an oxide layer on the channel region. Growing the oxide layer includes introducing a first source gas providing oxygen and introducing a second source gas providing hydrogen. The second source gas being different than the first source gas. The growing the oxide layer is grown by bonding the oxygen to a semiconductor element of the channel region to form the oxide layer and bonding the hydrogen to the semiconductor element of the channel region to form a semiconductor hydride byproduct. A gate dielectric layer and electrode can be formed over the oxide layer.

公开(公告)号：US20170207133A1

公开(公告)日：2017-07-20

申请号：US15001364

申请日：2016-01-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsiang-Pi Chang ,  Chih-Hao Wang ,  Wei-Hao Wu ,  Hung-Chang Sun ,  Lung-Kun Chu

IPC: H01L21/8238 ,  H01L29/49 ,  H01L27/092

CPC classification number: H01L21/823842 ,  H01L21/82345 ,  H01L27/092 ,  H01L29/4966

Abstract: The present disclosure relates to an integrated circuit with a work function metal layer disposed directly on a high-k dielectric layer, and an associated method of formation. In some embodiments, the integrated circuit is formed by forming a first work function metal layer directly on a high-k dielectric layer. Then the first work function metal layer is patterned to be left within a first gate region of a first device region and to be removed within a second gate region of a second device region. Thereby, the first work function metal layer is patterned directly on the high-k dielectric layer, using the high-k dielectric layer as an etch stop layer, and the patterning window is improved.

公开(公告)号：US11688812B2

公开(公告)日：2023-06-27

申请号：US17338426

申请日：2021-06-03

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chih-Yu Chang ,  Hsiang-Pi Chang ,  Zi-Wei Fang

IPC: H01L29/786 ,  H01L21/28 ,  H01L21/265 ,  H01L21/324 ,  H01L29/66 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423 ,  H01L29/49

CPC classification number: H01L29/78696 ,  H01L21/26513 ,  H01L21/28088 ,  H01L21/28185 ,  H01L21/28202 ,  H01L21/28238 ,  H01L21/324 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/42364 ,  H01L29/42392 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66636

Abstract: A method includes following steps. A silicon germanium layer is formed on a substrate. A surface layer of the silicon germanium layer is oxidized to form an interfacial layer comprising silicon oxide and germanium oxide. The interfacial layer is nitridated. A metal gate structure is formed over the nitridated interfacial layer.

公开(公告)号：US12166074B2

公开(公告)日：2024-12-10

申请号：US17651869

申请日：2022-02-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Weng Chang ,  Hsiang-Pi Chang ,  Huang-Lin Chao ,  Chung-Liang Cheng ,  Chi On Chui ,  Kun-Yu Lee ,  Tzer-Min Shen ,  Yen-Tien Tung ,  Chun-I Wu

IPC: H01L21/00 ,  H01L21/324 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

Abstract: A method includes removing a first dummy gate stack and a second dummy gate stack to form a first trench and a second trench. The first dummy gate stack and the second dummy gate stack are in a first device region and a second device region, respectively. The method further includes depositing a first gate dielectric layer and a second gate dielectric layer extending into the first trench and the second trench, respectively, forming a fluorine-containing layer comprising a first portion over the first gate dielectric layer, and a second portion over the second gate dielectric layer, removing the second portion, performing an annealing process to diffuse fluorine in the first portion into the first gate dielectric layer, and at a time after the annealing process, forming a first work-function layer and a second work-function layer over the first gate dielectric layer and the second gate dielectric layer, respectively.

公开(公告)号：US20240332091A1

公开(公告)日：2024-10-03

申请号：US18128119

申请日：2023-03-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shen-Yang LEE ,  Hsiang-Pi Chang ,  Huiching Chang ,  Shao An Wang ,  Kenichi Sano ,  Huang-Lin Chao

IPC: H01L21/8238 ,  H01L21/28 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L21/823842 ,  H01L21/28088 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/66439 ,  H01L29/775

Abstract: A semiconductor device and a method of fabricating the semiconductor device are disclosed. The method includes forming nanostructured channel regions, forming gate openings surrounding the nanostructured channel regions, forming oxide layers on exposed surfaces of the nanostructured channel regions in the gate openings, depositing a diffusion barrier layer on the oxide layers, depositing a first dielectric layer on the diffusion barrier layer, performing a doping process on the diffusion barrier layer and the first dielectric layer to form a doped diffusion barrier layer and a doped dielectric layer, and depositing a conductive layer on the doped dielectric layer.

公开(公告)号：US20240297239A1

公开(公告)日：2024-09-05

申请号：US18177911

申请日：2023-03-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shen-Yang LEE ,  Chun-Fu Lu ,  Hsiang-Pi Chang

IPC: H01L29/66 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/6656 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823468 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

Abstract: A semiconductor device and a method of fabricating the semiconductor device are disclosed. The method includes forming a fin base on a substrate, forming a superlattice structure including first and second nanostructured layers on the fin base, forming a polysilicon structure on the superlattice structure, epitaxially growing a S/D region on the fin base and adjacent to the first nanostructured layer, forming an oxygen-rich outer gate spacer including a first dielectric material with a first non-stoichiometric composition on a sidewall of the polysilicon structure, forming an oxygen-rich inner gate spacer including a second dielectric material with a second non-stoichiometric composition on a sidewall of the second nanostructured layer, and replacing the polysilicon structure with a gate structure.