公开(公告)号：US11581416B1

公开(公告)日：2023-02-14

申请号：US17406879

申请日：2021-08-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsiang-Pi Chang ,  Chung-Liang Cheng ,  I-Ming Chang ,  Yao-Sheng Huang ,  Huang-Lin Chao

IPC: H01L29/51 ,  H01L29/78 ,  H01L21/3115 ,  H01L21/8234 ,  H01L29/40

Abstract: A semiconductor device with different configurations of gate structures and a method of fabricating the same are disclosed. The method includes forming a fin structure on a substrate, forming a gate opening on the fin structure, forming an interfacial oxide layer on the fin structure, forming a first dielectric layer over the interfacial oxide layer, forming a dipole layer between the interfacial oxide layer and the first dielectric layer, forming a second dielectric layer on the first dielectric layer, forming a work function metal (WFM) layer on the second dielectric layer, and forming a gate metal fill layer on the WFM layer. The dipole layer includes ions of first and second metals that are different from each other. The first and second metals have electronegativity values greater than an electronegativity value of a metal or a semiconductor of the first dielectric layer.

公开(公告)号：US11145653B2

公开(公告)日：2021-10-12

申请号：US16585267

申请日：2019-09-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Liang Cheng ,  I-Ming Chang ,  Ziwei Fang ,  Huang-Lin Chao

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/78 ,  H01L21/02 ,  H01L29/66

Abstract: The present disclosure describes a semiconductor device that includes a semiconductor device that includes a first transistor having a first gate structure. The first gate structure includes a first gate dielectric layer doped with a first dopant at a first dopant concentration and a first work function layer on the first gate dielectric layer. The first gate structure also includes a first gate electrode on the first work function layer. The semiconductor device also includes a second transistor having a second gate structure, where the second gate structure includes a second gate dielectric layer doped with a second dopant at a second dopant concentration lower than the first dopant concentration. The second gate structure also includes a second work function layer on the second gate dielectric layer and a second gate electrode on the second work function layer.

公开(公告)号：US11024723B2

公开(公告)日：2021-06-01

申请号：US16920197

申请日：2020-07-02

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yao-Sheng Huang ,  Hung-Chang Sun ,  I-Ming Chang ,  Zi-Wei Fang

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/78 ,  H01L29/08 ,  H01L21/311 ,  H01L21/306

Abstract: A semiconductor includes a substrate, a semiconductor fin, an STI structure, a fin sidewall spacer, and a doped silicon layer. The semiconductor fin extends from the substrate. The STI structure laterally surrounds a lower portion of the semiconductor fin. The fin sidewall spacer extends along a middle portion of the semiconductor fin that is above the lower portion of the semiconductor fin. The doped silicon layer wraps around three sides of an upper portion of the semiconductor fin that is above the middle portion of the semiconductor fin.

公开(公告)号：US11018022B2

公开(公告)日：2021-05-25

申请号：US16035159

申请日：2018-07-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： I-Ming Chang ,  Chih-Cheng Lin ,  Chi-Ying Wu ,  Wei-Ming You ,  Ziwei Fang ,  Huang-Lin Chao

IPC: H01L21/335 ,  H01L21/8232 ,  H01L21/425 ,  H01L21/322 ,  H01L21/28 ,  H01L29/78 ,  H01L21/762 ,  H01L29/165 ,  H01L29/66

Abstract: A method for forming a semiconductor device structure is provided. The method includes depositing a gate dielectric layer over a substrate. The substrate has a base portion and a first fin portion over the base portion, and the gate dielectric layer is over the first fin portion. The method includes forming a gate electrode layer over the gate dielectric layer. The gate electrode layer includes fluorine. The method includes annealing the gate electrode layer and the gate dielectric layer so that fluorine from the gate electrode layer diffuses into the gate dielectric layer.

公开(公告)号：US11373910B2

公开(公告)日：2022-06-28

申请号：US16897229

申请日：2020-06-09

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yasutoshi Okuno ,  Cheng-Yi Peng ,  Ziwei Fang ,  I-Ming Chang ,  Akira Mineji ,  Yu-Ming Lin ,  Meng-Hsuan Hsiao

IPC: H01L21/8234 ,  H01L29/66 ,  H01L29/78 ,  H01L21/203 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/165 ,  H01L27/12 ,  H01L21/84 ,  H01L29/161

Abstract: A method of forming a semiconductor device including a fin field effect transistor (FinFET), the method includes forming a first sacrificial layer over a source/drain structure of a FinFET structure and an isolation insulating layer. The first sacrificial layer is patterned, thereby forming an opening. A first liner layer is formed on the isolation insulating layer in a bottom of the opening and on at least side faces of the patterned first sacrificial layer. After the first liner layer is formed, forming a dielectric layer in the opening. After the dielectric layer is formed, removing the patterned first sacrificial layer, thereby forming a contact opening over the source/drain structure. A conductive layer is formed in the contact opening. The FinFET is an n-type FET, and the source/drain structure includes an epitaxial layer made of Si1-y-a-bGeaSnbM2y, wherein 0

公开(公告)号：US11251087B2

公开(公告)日：2022-02-15

申请号：US16897234

申请日：2020-06-09

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yasutoshi Okuno ,  Cheng-Yi Peng ,  Ziwei Fang ,  I-Ming Chang ,  Akira Mineji ,  Yu-Ming Lin ,  Meng-Hsuan Hsiao

IPC: H01L21/8234 ,  H01L29/66 ,  H01L29/78 ,  H01L21/203 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/165 ,  H01L27/12 ,  H01L21/84 ,  H01L29/161

Abstract: A method of forming a semiconductor device including a fin field effect transistor (FinFET) includes forming a first sacrificial layer over a source/drain structure of a FinFET structure and an isolation insulating layer. The first sacrificial layer is patterned, thereby forming an opening. A first liner layer is formed on the isolation insulating layer in a bottom of the opening and on at least side faces of the patterned first sacrificial layer. After the first liner layer is formed, forming a dielectric layer in the opening. After the dielectric layer is formed, removing the patterned first sacrificial layer, thereby forming a contact opening over the source/drain structure. A conductive layer is formed in the contact opening. The FinFET is an n-type FET, and the source/drain structure includes an epitaxial layer including Si1−x−yM1xM2y, where M1 includes Sn, M2 is one or more of P and As, and 0.01≤x≤0.1, and 0.01≤y≤0.1.

公开(公告)号：US11177259B2

公开(公告)日：2021-11-16

申请号：US16585267

申请日：2019-09-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Liang Cheng ,  I-Ming Chang ,  Ziwei Fang ,  Huang-Lin Chao

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/78 ,  H01L21/02 ,  H01L29/66

Abstract: The present disclosure describes a semiconductor device that includes a semiconductor device that includes a first transistor having a first gate structure. The first gate structure includes a first gate dielectric layer doped with a first dopant at a first dopant concentration and a first work function layer on the first gate dielectric layer. The first gate structure also includes a first gate electrode on the first work function layer. The semiconductor device also includes a second transistor having a second gate structure, where the second gate structure includes a second gate dielectric layer doped with a second dopant at a second dopant concentration lower than the first dopant concentration. The second gate structure also includes a second work function layer on the second gate dielectric layer and a second gate electrode on the second work function layer.

公开(公告)号：US10685884B2

公开(公告)日：2020-06-16

申请号：US15665230

申请日：2017-07-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yasutoshi Okuno ,  Cheng-Yi Peng ,  Ziwei Fang ,  I-Ming Chang ,  Akira Mineji ,  Yu-Ming Lin ,  Meng-Hsuan Hsiao

IPC: H01L21/8234 ,  H01L29/66 ,  H01L29/78 ,  H01L21/203 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/165 ,  H01L27/12 ,  H01L21/84 ,  H01L29/161

Abstract: A semiconductor device includes a field effect transistor (FET). The FET includes a channel region and a source/drain region disposed adjacent to the channel region. The FET also includes a gate electrode disposed over the channel region. The FET is an n-type FET and the channel region is made of Si. The source/drain region includes an epitaxial layer including Si1-x-yM1xM2y, where M1 is one or more of Ge and Sn, and M2 is one or more of P and As, and 0.01≤x≤0.1.

公开(公告)号：US11908702B2

公开(公告)日：2024-02-20

申请号：US17406874

申请日：2021-08-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsiang-Pi Chang ,  Chung-Liang Cheng ,  I-Ming Chang ,  Yao-Sheng Huang ,  Huang-Lin Chao

IPC: H01L21/3115 ,  H01L29/66 ,  H01L29/78 ,  H01L21/477 ,  H01L21/02 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/51 ,  H01L27/092

CPC classification number: H01L21/3115 ,  H01L21/02192 ,  H01L21/477 ,  H01L21/823431 ,  H01L21/823857 ,  H01L27/0924 ,  H01L29/517 ,  H01L29/66795 ,  H01L29/7851

Abstract: A semiconductor device with different configurations of gate structures and a method of fabricating the same are disclosed. The method includes forming a fin structure on a substrate, forming a gate opening on the fin structure, forming a metallic oxide layer within the gate opening, forming a first dielectric layer on the metallic oxide layer, forming a second dielectric layer on the first dielectric layer, forming a work function metal (WFM) layer on the second dielectric layer, and forming a gate metal fill layer on the WFM layer. The forming the first dielectric layer includes depositing an oxide material with an oxygen areal density less than an oxygen areal density of the metallic oxide layer.

公开(公告)号：US10985265B2

公开(公告)日：2021-04-20

申请号：US16548446

申请日：2019-08-22

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chung-Liang Cheng ,  I-Ming Chang ,  Hsiang-Pi Chang ,  Hsueh-Wen Tsau ,  Ziwei Fang ,  Huang-Lin Chao

IPC: H01L29/66 ,  H01L29/78

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a semiconductor layer on a semiconductor substrate, forming an interfacial layer on the semiconductor layer, forming a first gate dielectric layer on the interfacial layer, introducing fluorine on the first gate dielectric layer, annealing the first gate dielectric layer, forming a second gate dielectric layer on the first gate dielectric layer, introducing fluorine on the second gate dielectric layer, annealing the second gate dielectric layer, and forming a gate stack structure on the second gate dielectric layer.