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公开(公告)号：US10482941B2
公开(公告)日：2019-11-19
申请号：US16128554
申请日：2018-09-12
Applicant: Toshiba Memory Corporation
Inventor： Takuya Shimada , Yasuaki Ootera , Tsuyoshi Kondo , Nobuyuki Umetsu , Michael Arnaud Quinsat , Masaki Kado , Susumu Hashimoto , Shiho Nakamura , Hideaki Aochi , Tomoya Sanuki , Shinji Miyano , Yoshihiro Ueda , Yuichi Ito , Yasuhito Yoshimizu
Abstract: According to one embodiment, a magnetic memory device includes a first memory portion, a first conductive portion, a first interconnection, and a controller. The first memory portion includes a first magnetic portion including a first portion and a second portion, a first magnetic layer, and a first nonmagnetic layer provided between the second portion and the first magnetic layer. The first conductive portion is electrically connected to the first portion. The first interconnection is electrically connected to the first magnetic layer. The controller is electrically connected to the first conductive portion and the first interconnection. The controller applies a first pulse having a first pulse height and a first pulse length between the first conductive portion and the first interconnection in a first write operation and applies a second pulse having a second pulse height and a second pulse length in a first shift operation.
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公开(公告)号：US10115733B2
公开(公告)日：2018-10-30
申请号：US15345790
申请日：2016-11-08
Applicant: Toshiba Memory Corporation
Inventor： Yoshiaki Fukuzumi , Shinya Arai , Masaki Tsuji , Hideaki Aochi , Hiroyasu Tanaka
IPC: H01L27/115 , H01L27/11582 , H01L29/66 , H01L29/792 , H01L27/11575 , H01L27/11565 , H01L29/423
Abstract: A semiconductor memory device includes a connecting member including a semiconductor material, a first electrode film, a first insulating film, a stacked body and three or more semiconductor pillars. The stacked body includes second electrode films and second insulating films that alternately stacked. The semiconductor pillars are arrayed along two or more directions, extend in a stacking direction, pierce through the stacked body and the first insulating film, and are connected to the connecting member. The device includes a third insulating film provided between the semiconductor pillars and the stacked body and between the connecting member and the first electrode film. A charge storage layer is provided at least between one of the second electrode films and the third insulating film.
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公开(公告)号：US10892269B2
公开(公告)日：2021-01-12
申请号：US16409637
申请日：2019-05-10
Applicant: Toshiba Memory Corporation
Inventor： Yoshiaki Fukuzumi , Hideaki Aochi , Mie Matsuo , Kenichiro Yoshii , Koichiro Shindo , Kazushige Kawasaki , Tomoya Sanuki
IPC: H01L27/11573 , H01L27/11568 , H01L27/11582 , H01L27/11575 , H01L25/065 , H01L25/18 , H01L21/18 , H01L21/768
Abstract: According to one embodiment, the array chip includes a three-dimensionally disposed plurality of memory cells and a memory-side interconnection layer connected to the memory cells. The circuit chip includes a substrate, a control circuit provided on the substrate, and a circuit-side interconnection layer provided on the control circuit and connected to the control circuit. The circuit chip is stuck to the array chip with the circuit-side interconnection layer facing to the memory-side interconnection layer. The bonding metal is provided between the memory-side interconnection layer and the circuit-side interconnection layer. The bonding metal is bonded to the memory-side interconnection layer and the circuit-side interconnection layer.
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公开(公告)号：US10658383B2
公开(公告)日：2020-05-19
申请号：US16519705
申请日：2019-07-23
Applicant: TOSHIBA MEMORY CORPORATION
Inventor： Yoshiaki Fukuzumi , Ryota Katsumata , Masaru Kito , Masaru Kidoh , Hiroyasu Tanaka , Yosuke Komori , Megumi Ishiduki , Junya Matsunami , Tomoko Fujiwara , Hideaki Aochi , Ryouhei Kirisawa , Yoshimasa Mikajiri , Shigeto Oota
IPC: H01L21/8249 , H01L27/11582 , H01L29/66 , H01L29/792 , H01L27/11578 , H01L21/223 , H01L21/265 , H01L29/78 , H01L29/04 , H01L29/16 , H01L29/423 , H01L29/49 , H01L29/10
Abstract: A nonvolatile semiconductor memory device, includes: a stacked structural unit including a plurality of insulating films alternately stacked with a plurality of electrode films in a first direction; a selection gate electrode stacked on the stacked structural unit in the first direction; an insulating layer stacked on the selection gate electrode in the first direction; a first semiconductor pillar piercing the stacked structural unit, the selection gate electrode, and the insulating layer in the first direction, a first cross section of the first semiconductor pillar having an annular configuration, the first cross section being cut in a plane orthogonal to the first direction; a first core unit buried in an inner side of the first semiconductor pillar, the first core unit being recessed from an upper face of the insulating layer; and a first conducting layer of the first semiconductor pillar provided on the first core unit to contact the first core unit.
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公开(公告)号：US20190287637A1
公开(公告)日：2019-09-19
申请号：US16120636
申请日：2018-09-04
Applicant: Toshiba Memory Corporation
Inventor： Michael Arnaud Quinsat , Yasuaki Ootera , Tsuyoshi Kondo , Nobuyuki Umetsu , Takuya Shimada , Masaki Kado , Susumu Hashimoto , Shiho Nakamura , Hideaki Aochi , Tomoya Sanuki , Shinji Myano , Yoshihiro Ueda , Yuichi Ito , Yasuhito Yoshimizu
Abstract: According to one embodiment, a magnetic memory device includes a first interconnect, a second interconnect, a first memory portion, and a controller. The first memory portion is provided between the first and second interconnects. The controller is electrically connected with the first and second interconnects. The first memory portion includes a first magnetic member, a first magnetic element, and a first non-linear element. The first magnetic element is provided between the first magnetic member and the second interconnect in a first current path between the first and second interconnects. The first non-linear element is provided between the first magnetic element and the second interconnect in the first current path. The controller is configured to supply a first shift current in the first current path in a first shift operation. The controller is configured to supply a first reading current in the first current path in a first reading operation.
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Patent Agency Ranking
公开(公告)号：US10311932B2
公开(公告)日：2019-06-04
申请号：US15918304
申请日：2018-03-12
Applicant: Toshiba Memory Corporation
Inventor： Nobuyuki Umetsu , Tsuyoshi Kondo , Yasuaki Ootera , Takuya Shimada , Michael Arnaud Quinsat , Masaki Kado , Susumu Hashimoto , Shiho Nakamura , Tomoya Sanuki , Yoshihiro Ueda , Yuichi Ito , Shinji Miyano , Hideaki Aochi , Yasuhito Yoshimizu
Abstract: According to one embodiment, a magnetic memory device includes a magnetic portion, a first magnetic layer, a first nonmagnetic layer, a first element portion, first to third interconnects, and a controller. In a first operation, the controller sets the first interconnect to a first potential, the second interconnect to a second potential, and the third interconnect to a third potential. An absolute value of a difference between the second potential and the third potential is greater than that between the first potential and the third potential. In a second operation, the controller sets the first interconnect to a fourth potential, the second interconnect to a fifth potential, and the third interconnect to a sixth potential. An absolute value of a difference between the fifth potential and the sixth potential is less than that between the fourth potential and the sixth potential.
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公开(公告)号：US20190088346A1
公开(公告)日：2019-03-21
申请号：US15919710
申请日：2018-03-13
Applicant: Toshiba Memory Corporation
Inventor： Yasuaki Ootera , Tsuyoshi Kondo , Nobuyuki Umetsu , Michael Arnaud Quinsat , Takuya Shimada , Masaki Kado , Susumu Hashimoto , Shiho Nakamura , Hideaki Aochi , Tomoya Sanuki , Shinji Miyano , Yoshihiro Ueda , Yuichi Ito , Yasuhito Yoshimizu
CPC classification number: G11C19/0841 , G11C19/28 , H01L27/228 , H01L43/08 , H01L43/10
Abstract: According to one embodiment, a magnetic memory device includes a first magnetic portion, a first magnetic layer, a first nonmagnetic layer, a second magnetic portion, a second magnetic layer, a second nonmagnetic layer, a first electrode, and a second electrode. The first magnetic portion includes a first magnetic part and a second magnetic part. The first nonmagnetic layer is provided between the first magnetic layer and the first magnetic part. The second magnetic portion includes a third magnetic part and a fourth magnetic part. The second nonmagnetic layer is provided between the second magnetic layer and the third magnetic part. The first electrode electrically is connected to the second magnetic part and the fourth magnetic part. The second electrode is electrically connected to the first magnetic part and the third magnetic part.
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公开(公告)号：US10163931B2
公开(公告)日：2018-12-25
申请号：US15960842
申请日：2018-04-24
Applicant: TOSHIBA MEMORY CORPORATION
Inventor： Yoshiaki Fukuzumi , Ryota Katsumata , Masaru Kidoh , Masaru Kito , Hiroyasu Tanaka , Yosuke Komori , Megumi Ishiduki , Hideaki Aochi
IPC: H01L27/10 , H01L29/51 , H01L27/11582 , H01L27/11573 , G11C16/04 , H01L27/11575 , H01L27/11578 , H01L27/105 , H01L27/11556 , H01L27/11551
Abstract: A non-volatile semiconductor storage device has a plurality of memory strings to each of which a plurality of electrically rewritable memory cells are connected in series. Each of the memory strings includes first semiconductor layers each having a pair of columnar portions extending in a vertical direction with respect to a substrate and a coupling portion formed to couple the lower ends of the pair of columnar portions; a charge storage layer formed to surround the side surfaces of the columnar portions; and first conductive layers formed to surround the side surfaces of the columnar portions and the charge storage layer. The first conductive layers function as gate electrodes of the memory cells.
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9.发明授权公开(公告)号：US10892270B2
公开(公告)日：2021-01-12
申请号：US16508577
申请日：2019-07-11
Applicant: Toshiba Memory Corporation
Inventor： Yoshiaki Fukuzumi , Hideaki Aochi
IPC: H01L27/11573 , H01L27/11582 , H01L25/18 , H01L27/11568 , H01L21/768 , H01L21/18 , H01L23/00
Abstract: According to one embodiment, the array chip includes a three-dimensionally disposed plurality of memory cells and a memory-side interconnection layer connected to the memory cells. The circuit chip includes a substrate, a control circuit provided on the substrate, and a circuit-side interconnection layer provided on the control circuit and connected to the control circuit. The circuit chip is stuck to the array chip with the circuit-side interconnection layer facing to the memory-side interconnection layer. The bonding metal is provided between the memory-side interconnection layer and the circuit-side interconnection layer. The bonding metal is bonded to the memory-side interconnection layer and the circuit-side interconnection layer.
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公开(公告)号：US10741583B2
公开(公告)日：2020-08-11
申请号：US16596892
申请日：2019-10-09
Applicant: Toshiba Memory Corporation
Inventor： Yoshiaki Fukuzumi , Shinya Arai , Masaki Tsuji , Hideaki Aochi , Hiroyasu Tanaka
IPC: H01L27/11582 , H01L29/66 , H01L29/792 , H01L27/11575 , H01L27/11565 , H01L29/423
Abstract: A semiconductor memory device includes a connecting member including a semiconductor material, a first electrode film, a first insulating film, a stacked body and three or more semiconductor pillars. The stacked body includes second electrode films and second insulating films that alternately stacked. The semiconductor pillars are arrayed along two or more directions, extend in a stacking direction, pierce through the stacked body and the first insulating film, and are connected to the connecting member. The device includes a third insulating film provided between the semiconductor pillars and the stacked body and between the connecting member and the first electrode film. A charge storage layer is provided at least between one of the second electrode films and the third insulating film.
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