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1.发明授权公开(公告)号：US06597754B1
公开(公告)日：2003-07-22
申请号：US09217233
申请日：1998-12-21
IPC分类号： H03D324
CPC分类号： H04L27/2275 , H03L7/093 , H03L7/0991 , H03L7/107 , H03L7/146 , H04B1/707 , H04L1/24 , H04L7/0334 , H04L27/22 , H04L27/2273 , H04L27/2277 , H04L2027/0028 , H04L2027/0046 , H04L2027/0067 , H04L2027/0069
摘要： A carrier-recovery loop for compensating frequency pulling in TDD and TDMA radio transceivers. The digital carrier-recovery loop includes a signal input, a digitally-controlled oscillator (DCO), a phase detector, a loop filter, and a memory. The memory stores an initializing value for the DCO, so that its frequency can be rapidly initialized at the start of a received frame. This initializing value is preferably either a sample of a control signal for the DCO, or a sample of the integrated value of a phase-error signal generated by the phase detector. Also described is a method for compensating the frequency pulling in a TDD or TDMA radio transceiver. The transceiver preferably receives data frames that have a preamble followed by a payload portion that holds the transmitted data. The method includes steps of (a) performing a carrier recovery during the preamble of a received frame, (b) storing a digital word indicative of a recovered carrier frequency at the end of the preamble, (c) continuing the carrier recovery during the payload portion of the received frame, (d) using the stored digital word to set an initial frequency for carrier recovery at the start of a subsequent frame, and (e) repeating said steps (a)-(d) for each frame in the series of data frames.
摘要翻译： 用于补偿TDD和TDMA无线电收发器中的频率牵引的载波恢复回路。 数字载波恢复回路包括信号输入，数字控制振荡器（DCO），相位检测器，环路滤波器和存储器。 存储器存储DCO的初始化值，使得其频率可以在接收帧的开始处被快速初始化。 该初始化值优选地是用于DCO的控制信号的采样或由相位检测器生成的相位误差信号的积分值的采样。 还描述了一种用于补偿TDD或TDMA无线电收发器中的频率牵引的方法。 收发器优选地接收具有前同步码的数据帧，后面是保存发送数据的有效载荷部分。 该方法包括以下步骤：（a）在接收到的帧的前导码中执行载波恢复，（b）在前导码的末尾存储指示恢复的载波频率的数字字，（c）在有效载荷期间继续载波恢复 （d）使用所存储的数字字来在后续帧的开始处设置用于载波恢复的初始频率，以及（e）对于该系列中的每个帧重复所述步骤（a） - （d） 的数据帧。
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公开(公告)号：US6018556A
公开(公告)日：2000-01-25
申请号：US968028
申请日：1997-11-12
IPC分类号： G06F11/00 , H03L7/093 , H03L7/099 , H03L7/107 , H03L7/14 , H03M13/00 , H04B1/707 , H04L1/24 , H04L7/033 , H04L27/00 , H04L27/22 , H04L27/227 , H03D3/24
CPC分类号： H04L27/2275 , H03L7/0991 , H03L7/107 , H03L7/146 , H04B1/707 , H04L1/24 , H04L27/22 , H04L27/2273 , H04L27/2277 , H03L7/093 , H04L2027/0028 , H04L2027/0046 , H04L2027/0067 , H04L2027/0069 , H04L7/0334
摘要： A digital loop filter in the carrier-recovery loop of a digital communications receiver. The recovery loop is a PLL that keeps the receiver oscillator locked to the carrier wave, and the loop filter provides control over the PLL's frequency response by conditioning an error signal that is fed back to the receiver oscillator. In the present invention, the error signal is a digital signal, and the loop filter is implemented in digital hardware. With this implementation the characteristics of the loop filter are determined by logic design rather than by physical features of analog components, thereby giving this filter a more precise function than one with analog integrators. This implementation is also immune to the low tolerances typical of the manufacturing process for analog devices (especially on monolithic circuits), and is more easily adjusted than its analog counterparts. Two gain coefficients characterize the loop filter in the present invention. These gain coefficients are chosen to be powers of two, simplifying the process of multiplying them with the digital error signal. The gain coefficients are read from a memory, making the loop filter easily programmable. By changing the gain coefficients during operation of the receiver, the carrier-recovery loop can be placed in one of the several operating modes, including acquisition, tracking, and hold. The receiver can be configured with the appropriate values of the gain coefficients for each operating mode during the initial assembly and during subsequent reconfigurations.
摘要翻译： 数字通信接收机的载波恢复回路中的数字环路滤波器。 恢复环路是将接收器振荡器锁定到载波的PLL，环路滤波器通过调节反馈到接收机振荡器的误差信号来提供对PLL频率响应的控制。 在本发明中，误差信号是数字信号，环路滤波器在数字硬件中实现。 通过这种实现，环路滤波器的特性由逻辑设计而不是模拟组件的物理特性决定，从而使得该滤波器比具有模拟积分器的功能更精确。 该实现也不受模拟器件（特别是单片电路）的制造工艺典型的低容差的影响，并且比其模拟器件更容易调整。 两个增益系数表征本发明中的环路滤波器。 这些增益系数被选为2的幂，简化了与数字误差信号相乘的过程。 从存储器读取增益系数，使得环路滤波器易于编程。 通过在接收机工作期间改变增益系数，载波恢复回路可以放置在几种操作模式之一，包括采集，跟踪和保持。 可以在初始组装期间和随后的重新配置期间，为每个操作模式的接收机配置适当的增益系数值。
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公开(公告)号：US6125139A
公开(公告)日：2000-09-26
申请号：US760883
申请日：1996-12-06
CPC分类号： H04M1/725 , G06F2213/0038 , H04M1/60
摘要： A digital cordless telecommunications unit that serves for communications when paired with a similar unit and connected with a network is disclosed. The unit receives analog receive voice signals and transmits analog transmit voice signals. In addition, the unit transmits digital baseband transmit signals and receives digital formatted baseband receive signals. The unit includes a baseband chip, as well as an audio functions circuit and a system control functions circuit. The audio functions circuit comprises an audio front end for receiving the analog receive voice signals and transmitting the analog transmit voice signals, and an adaptive differential pulse code modulator codec, connected to the audio front end, for converting the analog receive voice signals to the digital transmit signals and converting the digital formatted baseband receive signals to the analog transmit voice signals. The system control functions circuit comprises a microcontroller, connected to the codec, for controlling the baseband chip, a memory accessible by the microcontroller for storing control instructions, an interrupt controller connected to the microcontroller, a parallel port connected to the interrupt controller, a wake-up timer connected to the interrupt controller, a clock generator connected to the microcontroller, and a synchronous serial port connected to the interrupt controller.
摘要翻译： 公开了一种数字无绳电信单元，用于在与类似单元配对并与网络连接时用于通信。 该单元接收模拟接收语音信号并传输模拟传输语音信号。 此外，该单元发射数字基带发射信号并接收数字格式的基带接收信号。 该单元包括基带芯片，以及音频功能电路和系统控制功能电路。 音频功能电路包括用于接收模拟接收语音信号并发送模拟发送语音信号的音频前端，以及连接到音频前端的自适应差分脉冲编码调制器编解码器，用于将模拟接收语音信号转换成数字 发送信号并将数字格式的基带接收信号转换成模拟发送语音信号。 系统控制功能电路包括连接到编解码器的微控制器，用于控制基带芯片，由微控制器访问的用于存储控制指令的存储器，连接到微控制器的中断控制器，连接到中断控制器的并行端口，唤醒 - 连接到中断控制器的定时器，连接到微控制器的时钟发生器和连接到中断控制器的同步串行端口。
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公开(公告)号：US5978688A
公开(公告)日：1999-11-02
申请号：US726268
申请日：1996-10-04
CPC分类号： H04M1/733
摘要： A telephone for digital cordless telecommunications includes a frame formatter for logical channel formatting of transmitted baseband signals and received baseband signals. The telephone comprises a radio interface connection with the frame formatter, a FIFO/codec interface conductively coupled to the frame formatter, an interrupt interface conductively coupled to the frame formatter, a data control logic interface conductively coupled to the frame formatter, and a microcontroller interface conductively coupled to the frame formatter.
摘要翻译： 用于数字无绳电信的电话包括用于逻辑信道格式化发送的基带信号和接收的基带信号的帧格式化器。 电话包括与帧格式化器的无线电接口连接，导电耦合到帧格式化器的FIFO /编解码器接口，导电耦合到帧格式化器的中断接口，导电耦合到帧格式化器的数据控制逻辑接口和微控制器接口 导电地耦合到帧格式化器。
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公开(公告)号：US5923704A
公开(公告)日：1999-07-13
申请号：US740836
申请日：1996-11-04
申请人： Paul Schnizlein
发明人： Paul Schnizlein
CPC分类号： H03L7/0805 , H03L7/089 , H03L7/0992 , H04L7/0331
摘要： A method for generating transmit clock timing of a first communications unit of a communications system. The communications system includes the first communications unit and a second communications unit, each capable of communications with the other. The first communications unit has a first internal clock and the second communications unit has a second internal clock. According to one example embodiment, the method includes the steps of receiving a receive data signal by the first communications unit from the second communications unit, adjusting a receive reference clock to the receive data signal to generate an adjusted receive reference clock that tracks the receive data signal, accumulating the adjustments made in the adjusting step, applying the adjustments accumulated to vary the first internal clock in order to slave the first internal clock to the second internal clock of the second communications unit so as to generate an adjusted receive reference clock that is the adjusted and slaved first internal clock, and deriving a transmit clock from the adjusted receive reference clock.
摘要翻译： 一种用于产生通信系统的第一通信单元的发送时钟定时的方法。 通信系统包括第一通信单元和第二通信单元，每个通信单元能够彼此通信。 第一通信单元具有第一内部时钟，第二通信单元具有第二内部时钟。 根据一个示例性实施例，该方法包括以下步骤：从第二通信单元接收第一通信单元的接收数据信号，将接收参考时钟调整到接收数据信号，以产生跟踪接收数据的经调整的接收参考时钟 信号，累积在调整步骤中进行的调整，施加累积的调整以改变第一内部时钟，以使第一内部时钟从第二内部时钟到第二通信单元的第二内部时钟，以便生成调整后的接收参考时钟， 调整和从动的第一内部时钟，并从调整的接收参考时钟导出发送时钟。
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公开(公告)号：US5974584A
公开(公告)日：1999-10-26
申请号：US974966
申请日：1997-11-20
申请人： Alan Hendrickson , Paul Schnizlein
发明人： Alan Hendrickson , Paul Schnizlein
IPC分类号： G06F11/00 , H03L7/093 , H03L7/099 , H03L7/107 , H03L7/14 , H03M13/00 , H04B1/707 , H04L1/24 , H04L7/033 , H04L27/00 , H04L27/22 , H04L27/227
CPC分类号： H04L27/2275 , H03L7/0991 , H03L7/107 , H03L7/146 , H04B1/707 , H04L1/24 , H04L27/22 , H04L27/2273 , H04L27/2277 , H03L7/093 , H04L2027/0028 , H04L2027/0046 , H04L2027/0067 , H04L2027/0069 , H04L7/0334
摘要： In a digital communication system for voice signals, a system and method for improving the quality of a received signal. The invention comprises a system for arranging the data and parity bits in a data frame and a corresponding method for analyzing and using the received frames. In the present invention, the data are conveyed in short independent segments, such as one or a few ADPCM nibbles. The length of each segment is chosen to be short enough that the loss of one segment of data from the received signal does not significantly degrade the quality of the output analog signal. The transmitter generates a parity bit for each of these segments and composes transmit frames by alternating data segments with their corresponding parity bits. The receiver then receives each data segment along with its corresponding parity bit. This arrangement allows the receiver to identify specific received segments that contain errors, and minimizes the receiver's delay between receiving the segment and determining if contains an error. The invention also comprises a system and method for detecting such an erroneous segment and blanking it. If a received frame contains more than a threshold number of erroneous segments, then the remaining segments of the frame can be muted. Subsequent frames can then also be muted until one of the subsequent frames contains fewer than a second threshold number of errors.
摘要翻译： 在用于语音信号的数字通信系统中，提供接收信号质量的系统和方法。 本发明包括一种用于在数据帧中布置数据和奇偶校验位的系统以及用于分析和使用所接收帧的相应方法。 在本发明中，数据在短的独立段中传送，例如一个或几个ADPCM半字节。 每个段的长度被选择为足够短，使得来自接收信号的一段数据的丢失不会显着降低输出模拟信号的质量。 发射机为这些段中的每一个生成一个奇偶校验位，并通过交替的数据段与它们对应的奇偶校验位组成发送帧。 然后接收器接收每个数据段及其对应的奇偶校验位。 这种布置允许接收机识别包含错误的特定接收段，并且最小化接收机在接收段之间的延迟并确定是否包含错误。 本发明还包括用于检测这样的错误段并将其消隐的系统和方法。 如果接收到的帧包含多于阈值数量的错误段，则帧的剩余段可以被静音。 随后的帧也可以被静音，直到后续帧之一包含少于第二阈值数量的错误。
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公开(公告)号：US5898685A
公开(公告)日：1999-04-27
申请号：US914015
申请日：1997-08-01
申请人： Paul Schnizlein
发明人： Paul Schnizlein
CPC分类号： H04J3/0682 , H04M1/72505 , H04J3/0644
摘要： A time division multiplexed communications system is disclosed. The system includes multiple transceiver pairs. Each of the transceiver pairs operates according to its own timer. The transceiver pairs each include circuitry that synchronizes the respective timers to a common frequency signal supplied to each of the transceiver pairs. By so synchronizing the timer of each transceiver pair to a common frequency signal, transmissions of all the transceiver pairs in the system are synchronized. Synchronization of transmissions can reduce noise and interference between neighboring transceiver pairs.
摘要翻译： 公开了一种时分复用通信系统。 该系统包括多个收发器对。 每个收发器对根据自己的定时器运行。 收发机对各自包括将各个定时器同步到提供给每个收发器对的公共频率信号的电路。 通过将每个收发机对的定时器同步到公共频率信号，系统中所有收发器对的传输被同步。 传输的同步可以减少相邻收发器对之间的噪声和干扰。
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8.发明授权公开(公告)号：US06307480B1
公开(公告)日：2001-10-23
申请号：US08914017
申请日：1997-08-01
申请人： Peter Sheldon , Paul Schnizlein , Alan Hendrickson
发明人： Peter Sheldon , Paul Schnizlein , Alan Hendrickson
IPC分类号： G08B2100
CPC分类号： G06F1/28 , G06F1/24 , G06F1/30 , G06F11/0757 , H03K17/22
摘要： A reset circuit that incorporates a battery monitor and watchdog timer in an integrated circuit is disclosed. A battery monitor having an output indicative of a charge state of a battery and a watchdog timer having an output indicative of an operational state of software being executed by the integrated circuit are connected to reset logic having a reset signal output, wherein the reset logic generates a reset signal on the reset signal output if either the battery monitor output or the watchdog timer output is active.
摘要翻译： 公开了一种在集成电路中并入电池监视器和看门狗定时器的复位电路。 具有指示电池的充电状态的输出的电池监视器和具有指示由集成电路执行的软件的操作状态的输出的看门狗定时器被连接到具有复位信号输出的复位逻辑，其中复位逻辑产生 如果电池监视器输出或看门狗定时器输出有效，则复位信号输出上的复位信号。
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公开(公告)号：US6118384A
公开(公告)日：2000-09-12
申请号：US110798
申请日：1998-07-06
申请人： Peter Sheldon , Paul Schnizlein , Alan Hendrickson
发明人： Peter Sheldon , Paul Schnizlein , Alan Hendrickson
CPC分类号： G06F1/28 , G06F1/24 , G06F1/30 , H03K17/22 , G06F11/0757
摘要： A battery monitor with programmable voltage references. The battery monitor includes a comparator circuit connected to a battery for receiving a voltage level thereof and to a voltage reference circuit for receiving a at least one reference voltage generated thereby. A trim circuit is connected to the voltage reference circuit for adjusting the reference voltage(s) and generated by the voltage reference circuit. The comparator circuit compares the voltage level of the battery with the reference voltage(s) generates an output based on the relative value of the battery voltage compared to the reference voltage(s). The trim circuit is programmable and includes a microprocessor connected to a programmable register and a memory. The microprocessor obtains trim data from the memory and writes the trim data to the programmable register.
摘要翻译： 具有可编程参考电压的电池监视器。 电池监视器包括连接到用于接收其电压电平的电池的比较器电路和用于接收由此产生的至少一个参考电压的电压参考电路。 微调电路连接到电压参考电路，用于调整参考电压并由电压参考电路产生。 比较器电路将电池的电压与参考电压进行比较，基于与参考电压相比的电池电压的相对值来生成输出。 微调电路是可编程的，并且包括连接到可编程寄存器和存储器的微处理器。 微处理器从存储器中获得修剪数据，并将修剪数据写入可编程寄存器。
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公开(公告)号：US5943373A
公开(公告)日：1999-08-24
申请号：US581361
申请日：1995-12-29
申请人： Paul Schnizlein , Alan Hendrickson
发明人： Paul Schnizlein , Alan Hendrickson
CPC分类号： H04L7/10
摘要： A method for enabling communications between a first communications unit and a second communications unit. The first communications unit has a first crystal that provides first unit timing for that unit. The second communications unit has a second crystal that provides second unit timing for the second communications unit. The method includes the steps of receiving the first unit timing by the second communications unit, detecting a transition of a cycle of the first unit timing received, generating a reset pulse upon each detection of the transition of the cycle of the first timing unit received, and initiating a start-up of a new sequence of the second unit timing upon occurrence of the reset pulse. Operation according to the method allows for a wide variety of external protocols to be used with appropriate communications results.
摘要翻译： 一种用于实现第一通信单元和第二通信单元之间的通信的方法。 第一通信单元具有为该单元提供第一单元定时的第一晶体。 第二通信单元具有为第二通信单元提供第二单元定时的第二晶体。 该方法包括以下步骤：由第二通信单元接收第一单元定时，检测所接收的第一单位定时的周期的转变，在接收到的第一定时单元的周期的转变的每次检测时产生复位脉冲， 以及在复位脉冲发生时启动第二单元定时的新序列的启动。 根据该方法的操作允许使用各种外部协议以适当的通信结果。
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