公开(公告)号：US07750685B1

公开(公告)日：2010-07-06

申请号：US12251757

申请日：2008-10-15

申请人： Ryan Bunch ,  Stephen T. Janesch

发明人： Ryan Bunch ,  Stephen T. Janesch

IPC分类号： H03K9/06 ,  H03D3/00

CPC分类号： H03L7/087 ,  H03L7/099 ,  H03L7/10 ,  H03L7/18 ,  H03L2207/12

摘要： A first embodiment of the present invention relates to a frequency and phase locked loop (FPLL) synthesizer having a frequency-locked loop (FLL) operating mode and a phase-locked loop (PLL) operating mode. The FLL operating mode is used for rapid coarse tuning of the FPLL synthesizer and is followed by the PLL operating mode for fine tuning and stabilization of the frequency of an output signal from the FPLL synthesizer. A second embodiment of the present invention relates to a high resolution frequency measurement circuit that is capable of directly measuring the frequency of a high frequency signal to provide a high resolution frequency measurement using a lower frequency reference signal, and may include linear feedback shift register (LFSR) circuitry and LFSR-to-binary conversion circuitry. A third embodiment of the present invention relates to an FPLL having an FLL that includes the high resolution frequency measurement circuit.

摘要翻译： 本发明的第一实施例涉及具有锁相环（FLL）操作模式和锁相环（PLL）操作模式的频率和锁相环（FPLL）合成器。 FLL操作模式用于FPLL合成器的快速粗调，后跟PLL操作模式，用于微调和稳定来自FPLL合成器的输出信号的频率。 本发明的第二实施例涉及一种高分辨率频率测量电路，其能够直接测量高频信号的频率以使用较低频率参考信号提供高分辨率频率测量，并且可以包括线性反馈移位寄存器 LFSR）电路和LFSR至二进制转换电路。 本发明的第三实施例涉及一种具有包括高分辨率频率测量电路的FLL的FPLL。

公开(公告)号：US06518801B1

公开(公告)日：2003-02-11

申请号：US09368172

申请日：1999-08-05

申请人： Stephen T. Janesch

发明人： Stephen T. Janesch

IPC分类号： H03B2100

CPC分类号： G06F1/025

摘要： The present invention provides an improved apparatus and technique for removing alias signals from the output of a discretely timed circuit. Rather than simply lowpass filtering an output signal from a discretely timed circuit signal to remove aliases as in conventional discretely timed circuits, and instead of increasing the frequency of the clock signal in other conventional discretely timed circuits, the present invention provides for interpolation between clock edges, taking advantage of information in the digital representation, to reduce or eliminate many lower-order alias signal components. More particularly, the present invention eliminates lower-order aliases of a discretely timed circuit, e.g., of a 1-bit resolution direct digital synthesizer (DDS) by interpolating transitions within clock periods utilizing the period of the signal and its instantaneous phase, to improve the time resolution of the output signal. In a disclosed embodiment, a multiplier produces product of an output signal (e.g., from a phase accumulator) and its period (e.g., output from a period register). The disclosed interpolator includes a digital comparator and a varying reference generator, e.g., a ramp generator, together with an appropriate digital-to-analog converter, to set a threshold proportional to the phase-period product. If the product of the multiplier is greater than unity, a transition is prohibited. However, if the product of the multiplier is less than or equal to unity, a transition occurs, preferably within the next clock period.

摘要翻译： 本发明提供一种用于从离散定时电路的输出中去除别名信号的改进的装置和技术。 而不是简单地对来自离散定时电路信号的输出信号进行低通滤波以去除常规离散定时电路中的别名，而不是增加其它常规离散定时电路中的时钟信号的频率，本发明提供时钟沿 利用数字表示中的信息来减少或消除许多低阶别名信号分量。 更具体地说，本发明通过使用信号周期及其瞬时相位在时钟周期内插入转换来消除例如1位分辨率直接数字合成器（DDS）的离散定时电路的低阶别名，以改善 输出信号的时间分辨率。 在公开的实施例中，乘法器产生输出信号（例如，来自相位累加器）及其周期（例如，来自周期寄存器的输出）的乘积。 所公开的插值器包括数字比较器和变化的参考发生器，例如斜坡发生器以及适当的数模转换器，以设置与相位周期乘积成比例的阈值。 如果乘法器的乘积大于单位，则禁止转换。 然而，如果乘法器的乘积小于或等于1，则发生转换，优选在下一个时钟周期内。

公开(公告)号：US6072842A

公开(公告)日：2000-06-06

申请号：US968029

申请日：1997-11-12

申请人： Stephen T. Janesch ,  Paul G. Schnizlein ,  Ed Bell

发明人： Stephen T. Janesch ,  Paul G. Schnizlein ,  Ed Bell

IPC分类号： H03L7/093 ,  H03L7/099 ,  H03L7/14 ,  H04L1/24 ,  H04L7/033 ,  H04L27/00 ,  H04L27/22 ,  H04L27/227 ,  H03D3/24

CPC分类号： H04L27/22 ,  H03L7/0991 ,  H03L7/146 ,  H04L1/24 ,  H04L27/2273 ,  H03L7/093 ,  H04L2027/0028 ,  H04L2027/0046 ,  H04L2027/0067 ,  H04L2027/0069 ,  H04L7/0334

摘要： A carrier-recovery loop for a receiver in a communication system with features that facilitate initialization of the loop. The carrier-recovery loop is a PLL that uses a feedback signal to keep a recovery oscillator phase-locked to the carrier of a received signal. In the present invention, an initializing value of the feedback signal is stored in a memory and provided to a digitally controlled recovery oscillator (DCO). This initializing value brings the recovered signal to an initial frequency that approximates the carrier frequency. When the receivers starts to acquire a phase-lock with the carrier, the carrier-recovery loop is in a condition close to the desired phase lock. Preparing the DCO in this manner imparts a significant improvement to the carrier-recovery loop. The response time for the loop to acquire a phase lock depends in part on its initial frequency offset from the carrier. In general, reducing this initial offset reduces the loop's acquisition time. By thus anticipating the frequency of the carrier, this carrier-recovery loop can have an improved acquisition time to reach phase lock. The initializing value of the feedback signal can be generated by recording a sample of the feedback signal when the carrier-recovery loop is phase-locked to a received signal or to an on-board crystal oscillator. The invention also includes a mechanism to correct drifts in the crystal oscillator's frequency.

摘要翻译： 具有促进循环初始化的特征的通信系统中的接收机的载波恢复回路。 载波恢复环路是使用反馈信号将恢复振荡器锁相到接收信号的载波的PLL。 在本发明中，将反馈信号的初始化值存储在存储器中并提供给数字控制的恢复振荡器（DCO）。 该初始化值使恢复的信号达到近似载波频率的初始频率。 当接收机开始与载波采集相位锁定时，载波恢复环路处于接近所需相位锁定状态。 以这种方式准备DCO对载体恢复循环有显着的改进。 环路获取锁相的响应时间部分取决于其与载波的初始频率偏移。 一般来说，减少初始偏移可以减少环路的采集时间。 通过这样预期载波的频率，该载波恢复回路可以具有改善的采集时间以达到锁相。 反馈信号的初始化值可以通过当载波恢复环路锁相到接收信号时记录反馈信号的样本，或者通过在板上晶体振荡器上记录反馈信号的初始化值。 本发明还包括校正晶体振荡器频率漂移的机制。

公开(公告)号：US07626462B1

公开(公告)日：2009-12-01

申请号：US11415578

申请日：2006-05-02

申请人： Alexander Wayne Hietala ,  Ryan Lee Bunch ,  Scott Robert Humphreys ,  Barry Travis Hunt, Jr. ,  Stephen T. Janesch

发明人： Alexander Wayne Hietala ,  Ryan Lee Bunch ,  Scott Robert Humphreys ,  Barry Travis Hunt, Jr. ,  Stephen T. Janesch

IPC分类号： H03L7/00

CPC分类号： H03L7/23 ,  H03J1/005 ,  H03J7/065 ,  H03L7/1974

摘要： A fractional-N based Automatic Frequency Control (AFC) system for a mobile terminal is provided. In general, automatic frequency control is implemented in a frequency synthesizer to correct or compensate for a frequency error of an associated reference oscillator. The frequency synthesizer includes a first fractional-N phase-locked loop (FN-PLL) generating a baseband clock signal used by a baseband processor of the mobile terminal, a second FN-PLL generating a receiver local oscillator signal used by a receiver of the mobile terminal to downconvert a received radio frequency signal to a desired frequency, and a translational PLL generating a transmitter local oscillator signal used by a transmitter of the mobile terminal to provide a radio frequency transmit signal. The automatic frequency control is performed by applying a digital correction value, which is preferably multiplicative, to fractional-N dividers of the first and second FN-PLLs.

摘要翻译： 提供了一种用于移动终端的基于分数N的自动频率控制（AFC）系统。 通常，在频率合成器中实现自动频率控制以校正或补偿相关参考振荡器的频率误差。 频率合成器包括产生由移动终端的基带处理器使用的基带时钟信号的第一小数N锁相环（FN-PLL），第二FN-PLL产生由接收机使用的接收机本地振荡器信号 移动终端将所接收的射频信号下变频到期望的频率，以及平移PLL，其生成由移动终端的发射机使用以提供射频发射信号的发射机本地振荡器信号。 通过将优选乘法的数字校正值应用于第一和第二FN-PLL的分数N分频器来执行自动频率控制。

公开(公告)号：US06198353B1

公开(公告)日：2001-03-06

申请号：US09368493

申请日：1999-08-05

申请人： Stephen T. Janesch ,  Carl R. Stevenson

发明人： Stephen T. Janesch ,  Carl R. Stevenson

IPC分类号： H03L7085

CPC分类号： H03L7/085 ,  H03L7/1806

摘要： A digital phase locked loop (PLL) frequency synthesizer having the conventional voltage controlled oscillator (VCO) divider in the feedback loop to the phase detector replaced with a direct digital synthesizer (DDS) divider. In accordance with the principles of the present invention, the reference divider in the input path may also be replaced with a DDS divider. Moreover, a new architecture for the phase detector and current digital-to-analog converter (DAC) which operate on the instantaneous phase of each DDS is provided. Thus, in accordance with the principles of the present invention, the update rate of the digital PLL frequency synthesizer is not based on the frequency signal output from the reference divider in the input path (as in conventional digital PLL frequency synthesizer architectures). Rather, the update rate is based on fixed clock signals output from the clock generator, which utilizes the master clock and the output frequency, in accordance with the principles of the present invention. The digital PLL frequency synthesizer is capable of a very high update rate, very fast settling time, and very fine frequency control.

摘要翻译： 数字锁相环（PLL）频率合成器具有在直接数字合成器（DDS）分频器中的相位检测器的反馈回路中的常规压控振荡器（VCO）分频器。 根据本发明的原理，输入路径中的参考分压器也可以用DDS分压器代替。 此外，还提供了在每个DDS的瞬时相位上操作的相位检测器和当前数模转换器（DAC）的新架构。 因此，根据本发明的原理，数字PLL频率合成器的更新速率不是基于从输入路径中的参考分频器输出的频率信号（如在常规数字PLL频率合成器架构中）。 相反，根据本发明的原理，更新速率基于从时钟发生器输出的固定时钟信号，其利用主时钟和输出频率。 数字PLL频率合成器具有非常高的更新速率，非常快的建立时间和非常精细的频率控制。

公开(公告)号：US07898343B1

公开(公告)日：2011-03-01

申请号：US12341638

申请日：2008-12-22

申请人： Stephen T. Janesch

发明人： Stephen T. Janesch

IPC分类号： H03L7/00

CPC分类号： H03L7/087 ,  H03L7/0891 ,  H03L7/093 ,  H03L7/099 ,  H03L7/113 ,  H03L7/1974 ,  H03L2207/06 ,  H03L2207/12

摘要： The present invention relates to a calibrated phase-locked loop (PLL), which has a calibration mode for measuring a tuning gain of a variable frequency oscillator (VFO) and a PLL mode for normal operation. Calibration information based on the tuning gain is used during the PLL mode to regulate a PLL loop gain. During the calibration mode, the calibrated PLL operates as a frequency-locked loop (FLL) for low frequency lock times, and during the PLL mode the calibrated PLL operates as a PLL for high frequency accuracy and low noise. By regulating the PLL loop gain, the desired noise spectrum and dynamic behavior of the PLL may be maintained in spite of variations in the operating characteristics or in the characteristics of the PLL components.

摘要翻译： 本发明涉及校准锁相环（PLL），其具有用于测量可变频率振荡器（VFO）的调谐增益的校准模式和用于正常操作的PLL模式。 在PLL模式下，使用基于调谐增益的校准信息来调节PLL环路增益。 在校准模式下，校准PLL作为低频锁定时间的锁相环（FLL）工作，在PLL模式下，校准后的PLL作为PLL工作，可实现高频精度和低噪声。 通过调节PLL环路增益，尽管操作特性或PLL组件的特性有所变化，仍可保持PLL的期望噪声谱和动态特性。

公开(公告)号：US06650721B1

公开(公告)日：2003-11-18

申请号：US09368583

申请日：1999-08-05

申请人： Stephen T. Janesch ,  Carl R. Stevenson

发明人： Stephen T. Janesch ,  Carl R. Stevenson

IPC分类号： H03D324

CPC分类号： H03C3/095 ,  H03L7/0891 ,  H03L7/1806

摘要： A digital phase locked loop (PLL) frequency synthesizer includes a 1-bit numerically controlled oscillator (NCO) to negate the requirement that a VCO frequency be an integer multiple of its reference frequency. Thus, in accordance with the principles of the present invention, a direct digital synthesizer (DDS) or numerically controlled oscillator (NCO) is used to form a frequency divider in a feedback path of a PLL. Thus, a synthesizer with fine frequency control and very fast settling time is disclosed. The conventional integer-ratio relationship between the reference frequency fREF and the synthesized output frequency signal fVCO is overcome by replacement of a conventional VCO divider in a feedback path of a digital PLL with a 1-bit NCO. This allows the reference frequency fREF to be greater than the channel spacing, i.e., the channel spacing can be smaller than the reference frequency fREF. Thus, a much quicker settling time and improved VCO phase noise are provided, either of which results in a significant improvement in the performance of virtually any communications system.

摘要翻译： 数字锁相环（PLL）频率合成器包括1位数控振荡器（NCO），以消除VCO频率为其参考频率的整数倍的要求。 因此，根据本发明的原理，使用直接数字合成器（DDS）或数控振荡器（NCO）在PLL的反馈路径中形成分频器。 因此，公开了具有精细频率控制和非常快的建立时间的合成器。 参考频率fREF和合成输出频率信号fVCO之间的常规整数比关系通过用具有1位NCO的数字PLL的反馈路径中的常规VCO分频器的替代来克服。 这允许参考频率fREF大于信道间隔，即，信道间隔可以小于参考频率f REF。 因此，提供了更快的建立时间和改进的VCO相位噪声，其中任何一个导致几乎任何通信系统的性能的显着改善。

公开(公告)号：US06597754B1

公开(公告)日：2003-07-22

申请号：US09217233

申请日：1998-12-21

申请人： Stephen T. Janesch ,  Paul Schnizlein

发明人： Stephen T. Janesch ,  Paul Schnizlein

IPC分类号： H03D324

CPC分类号： H04L27/2275 ,  H03L7/093 ,  H03L7/0991 ,  H03L7/107 ,  H03L7/146 ,  H04B1/707 ,  H04L1/24 ,  H04L7/0334 ,  H04L27/22 ,  H04L27/2273 ,  H04L27/2277 ,  H04L2027/0028 ,  H04L2027/0046 ,  H04L2027/0067 ,  H04L2027/0069

摘要： A carrier-recovery loop for compensating frequency pulling in TDD and TDMA radio transceivers. The digital carrier-recovery loop includes a signal input, a digitally-controlled oscillator (DCO), a phase detector, a loop filter, and a memory. The memory stores an initializing value for the DCO, so that its frequency can be rapidly initialized at the start of a received frame. This initializing value is preferably either a sample of a control signal for the DCO, or a sample of the integrated value of a phase-error signal generated by the phase detector. Also described is a method for compensating the frequency pulling in a TDD or TDMA radio transceiver. The transceiver preferably receives data frames that have a preamble followed by a payload portion that holds the transmitted data. The method includes steps of (a) performing a carrier recovery during the preamble of a received frame, (b) storing a digital word indicative of a recovered carrier frequency at the end of the preamble, (c) continuing the carrier recovery during the payload portion of the received frame, (d) using the stored digital word to set an initial frequency for carrier recovery at the start of a subsequent frame, and (e) repeating said steps (a)-(d) for each frame in the series of data frames.

摘要翻译： 用于补偿TDD和TDMA无线电收发器中的频率牵引的载波恢复回路。 数字载波恢复回路包括信号输入，数字控制振荡器（DCO），相位检测器，环路滤波器和存储器。 存储器存储DCO的初始化值，使得其频率可以在接收帧的开始处被快速初始化。 该初始化值优选地是用于DCO的控制信号的采样或由相位检测器生成的相位误差信号的积分值的采样。 还描述了一种用于补偿TDD或TDMA无线电收发器中的频率牵引的方法。 收发器优选地接收具有前同步码的数据帧，后面是保存发送数据的有效载荷部分。 该方法包括以下步骤：（a）在接收到的帧的前导码中执行载波恢复，（b）在前导码的末尾存储指示恢复的载波频率的数字字，（c）在有效载荷期间继续载波恢复 （d）使用所存储的数字字来在后续帧的开始处设置用于载波恢复的初始频率，以及（e）对于该系列中的每个帧重复所述步骤（a） - （d） 的数据帧。

公开(公告)号：US06532270B1

公开(公告)日：2003-03-11

申请号：US09212903

申请日：1998-12-16

申请人： Eddy Kent Bell ,  Javier V. Magaña ,  Stephen T. Janesch

发明人： Eddy Kent Bell ,  Javier V. Magaña ,  Stephen T. Janesch

IPC分类号： H03C152

CPC分类号： H03C3/40 ,  H04B1/28

摘要： In the broadcast band having a plurality of channels allocated therein, by using high-side injection and low-side injection as described herein, the noise introduced into the channel by the local oscillator signal can be minimized. The local oscillator signal in combination with the intermediate frequency determines the frequency of the channel signal being produced by the transmitter. The selected high-or low-side injection determines whether the bulk of the power is introduced into the combination frequency signal (i.e., the channel) above or below the local oscillator frequency, thereby moving the local oscillator frequency outside the broadcast band. The non-selected sideband is even further outside broadcast band.

摘要翻译： 在其中分配有多个信道的广播频带中，通过使用如本文所述的高侧注入和低侧注入，可以将通过本地振荡器信号引入信道的噪声最小化。 本地振荡器信号与中频组合确定由发射机产生的信道信号的频率。 所选择的高侧或低侧喷射确定大部分功率是否被引入到本地振荡器频率之上或之下的组合频率信号（即，信道）中，从而将本地振荡器频率移动到广播频带之外。 未选择的边带甚至在广播频带之外。

公开(公告)号：US6018556A

公开(公告)日：2000-01-25

申请号：US968028

申请日：1997-11-12

申请人： Stephen T. Janesch ,  Paul Schnizlein

发明人： Stephen T. Janesch ,  Paul Schnizlein

IPC分类号： G06F11/00 ,  H03L7/093 ,  H03L7/099 ,  H03L7/107 ,  H03L7/14 ,  H03M13/00 ,  H04B1/707 ,  H04L1/24 ,  H04L7/033 ,  H04L27/00 ,  H04L27/22 ,  H04L27/227 ,  H03D3/24

CPC分类号： H04L27/2275 ,  H03L7/0991 ,  H03L7/107 ,  H03L7/146 ,  H04B1/707 ,  H04L1/24 ,  H04L27/22 ,  H04L27/2273 ,  H04L27/2277 ,  H03L7/093 ,  H04L2027/0028 ,  H04L2027/0046 ,  H04L2027/0067 ,  H04L2027/0069 ,  H04L7/0334

摘要： A digital loop filter in the carrier-recovery loop of a digital communications receiver. The recovery loop is a PLL that keeps the receiver oscillator locked to the carrier wave, and the loop filter provides control over the PLL's frequency response by conditioning an error signal that is fed back to the receiver oscillator. In the present invention, the error signal is a digital signal, and the loop filter is implemented in digital hardware. With this implementation the characteristics of the loop filter are determined by logic design rather than by physical features of analog components, thereby giving this filter a more precise function than one with analog integrators. This implementation is also immune to the low tolerances typical of the manufacturing process for analog devices (especially on monolithic circuits), and is more easily adjusted than its analog counterparts. Two gain coefficients characterize the loop filter in the present invention. These gain coefficients are chosen to be powers of two, simplifying the process of multiplying them with the digital error signal. The gain coefficients are read from a memory, making the loop filter easily programmable. By changing the gain coefficients during operation of the receiver, the carrier-recovery loop can be placed in one of the several operating modes, including acquisition, tracking, and hold. The receiver can be configured with the appropriate values of the gain coefficients for each operating mode during the initial assembly and during subsequent reconfigurations.

摘要翻译： 数字通信接收机的载波恢复回路中的数字环路滤波器。 恢复环路是将接收器振荡器锁定到载波的PLL，环路滤波器通过调节反馈到接收机振荡器的误差信号来提供对PLL频率响应的控制。 在本发明中，误差信号是数字信号，环路滤波器在数字硬件中实现。 通过这种实现，环路滤波器的特性由逻辑设计而不是模拟组件的物理特性决定，从而使得该滤波器比具有模拟积分器的功能更精确。 该实现也不受模拟器件（特别是单片电路）的制造工艺典型的低容差的影响，并且比其模拟器件更容易调整。 两个增益系数表征本发明中的环路滤波器。 这些增益系数被选为2的幂，简化了与数字误差信号相乘的过程。 从存储器读取增益系数，使得环路滤波器易于编程。 通过在接收机工作期间改变增益系数，载波恢复回路可以放置在几种操作模式之一，包括采集，跟踪和保持。 可以在初始组装期间和随后的重新配置期间，为每个操作模式的接收机配置适当的增益系数值。