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公开(公告)号：US20160182262A1
公开(公告)日：2016-06-23
申请号：US14577885
申请日：2014-12-19
Applicant: Intel Corporation
Inventor： Andreas Jörn Leistner , Georgios Palaskas
CPC classification number: H04L25/08 , G06F1/025 , H04B15/06 , H04J11/0063 , H04J2011/0096 , H04L7/0091 , H04L7/0331 , H04L27/122
Abstract: Apparatus and methods for disrupting or preventing periodicity in DTC circuits are provided. In an example, a communication circuit can include a digital-to-time converter (DTC) and a processing path coupled to the DTC. The DTC can be configured to receive reference information, modulation information and first dither information, and to provide a modulated signal using the reference information, the modulation information and the first dither information. The processing path can be configured to receive second dither information and to cancel the first dither information using the second dither information, wherein the DTC is configured to disrupt processing periodicity of the communication circuit using the first dither information.
Abstract translation: 提供了在DTC电路中破坏或防止周期性的装置和方法。 在一个示例中，通信电路可以包括数字 - 时间转换器（DTC）和耦合到DTC的处理路径。 DTC可以被配置为接收参考信息，调制信息和第一抖动信息，并且使用参考信息，调制信息和第一抖动信息来提供调制信号。 处理路径可以被配置为接收第二抖动信息并且使用第二抖动信息来取消第一抖动信息，其中DTC被配置为使用第一抖动信息来中断通信电路的处理周期。
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公开(公告)号：US08890595B2
公开(公告)日：2014-11-18
申请号：US13895849
申请日：2013-05-16
Applicant: Fmax Technologies, Inc.
Inventor： Iain Ross Mactaggart
Abstract: Embodiments of a device and circuit implementing a digitally controlled oscillator with reduced analog components. In an example, the digitally controlled oscillator can include a phase accumulator controlled by a stall circuit to selective stall the phase accumulator. In some examples, the digitally controlled oscillator can include a phase select circuit to select multiple phases of a phase select circuit based on the output of the phase accumulator. In some examples, these selected phases can then be used by a phase interpolator to generate a synthetic clock signal.
Abstract translation: 实现具有减少的模拟组件的数字控制振荡器的装置和电路的实施例。 在一个示例中，数字控制振荡器可以包括由失速电路控制的相位累加器，以选择性地停止相位累加器。 在一些示例中，数控振荡器可以包括基于相位累加器的输出来选择相位选择电路的多个相位的相位选择电路。 在一些示例中，这些选择的相位然后可以由相位内插器使用以产生合成时钟信号。
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3.发明授权公开(公告)号：US08878715B2
公开(公告)日：2014-11-04
申请号：US13776371
申请日：2013-02-25
Applicant: Kabushiki Kaisha Toshiba
Inventor： Daisuke Miyashita
CPC classification number: H03M1/50 , G04F10/005 , G06F1/025 , H03M1/822
Abstract: A time-to-digital converting circuit includes a first flip-flop and a second flip-flop. The time-to-digital converting circuit a first delay controlling circuit that outputs a first data signal obtained by controlling a delay time of the reference data signal input thereto via the first signal input terminal based on the first output signal and a first clock signal obtained by controlling a delay time of the reference clock signal input thereto via the second signal input terminal based on the first output signal.
Abstract translation: 时间数字转换电路包括第一触发器和第二触发器。 时间数字转换电路，第一延迟控制电路，其输出通过基于第一输出信号控制经由第一信号输入端子输入的参考数据信号的延迟时间和获得的第一时钟信号而获得的第一数据信号 通过基于第一输出信号，经由第二信号输入端子控制输入到其的基准时钟信号的延迟时间。
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4.发明授权Systems and methods for precise generation of phase variation in digital signals 有权用于精确生成数字信号相位变化的系统和方法公开(公告)号：US08850259B2
公开(公告)日：2014-09-30
申请号：US12930490
申请日：2011-01-07
Applicant: Charles A. Webb, III
Inventor： Charles A. Webb, III
CPC classification number: G06F1/025 , G06F1/0321
Abstract: Systems and methods are disclosed for precise generation of phase variation in digital signals. The disclosed signal generation embodiments generate a pattern of information bits that represents a digital signal with desired phase variations and transmit this digital pattern at high speed utilizing a serializer to generate a high speed bit stream. The high speed bit stream can be used to generate one or more digital signals, such as clock signals, having desired rates and desired phase variations. In certain embodiments, the desired phase variation can be introduced into the resulting digital signal by removing and/or inserting bits in a digital pattern thereby moving logic transitions (e.g., rising edge transitions, falling edge transitions) as desired within the resulting digital signal. In addition to clock signals, the resulting digital signals generated can be control signals, data signals and/or any other desired digital signal.
Abstract translation: 公开了用于在数字信号中精确地产生相位变化的系统和方法。 所公开的信号生成实施例产生表示具有期望的相位变化的数字信号的信息比特的模式，并且利用串行器高速地传送该数字模式以生成高速比特流。 高速比特流可用于产生具有期望速率和期望相位变化的一个或多个数字信号，例如时钟信号。 在某些实施例中，可以通过去除和/或插入数字图形中的位来将期望的相位变化引入到所得数字信号中，从而根据期望在所得到的数字信号中移动逻辑转换（例如，上升沿转变，下降沿转换）。 除了时钟信号之外，所生成的数字信号可以是控制信号，数据信号和/或任何其它所需的数字信号。
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5.发明授权Digital forced oscilation by direct digital synthesis to generate pulse stream having frequency relative to a reference clock signal and to eliminate an off-chip filter 有权通过直接数字合成数字强制振荡，产生具有相对于参考时钟信号的频率的脉冲串，并消除片外滤波器公开(公告)号：US08732510B2
公开(公告)日：2014-05-20
申请号：US13117054
申请日：2011-05-26
Applicant: Martin Mallinson
Inventor： Martin Mallinson
Abstract: An opportunity is apparent to develop alternative circuitry. Simplified circuitry without artifacts tied to the clock that drives a digital frequency generator (DFG) is useful in a variety of tunable electronic devices. The present invention relates to digital frequency generation. In particular, it relates to a method and apparatus for the digital generation of a pulse stream having a desired frequency relative to a reference clock signal and the ratio of two integers. The method applies generally to integers whose ratio is not an integer. The DFG as a device can be integrated onto a simple chip, without need for an off-chip filter.
Abstract translation: 开发替代电路的机会很明显。 与驱动数字频率发生器（DFG）的时钟相关的无伪影的简化电路在各种可调电子设备中非常有用。 本发明涉及数字频率产生。 特别地，本发明涉及一种用于数字生成具有相对于参考时钟信号的期望频率和两个整数的比率的脉冲流的方法和装置。 该方法通常适用于其比率不是整数的整数。 作为设备的DFG可以集成到简单的芯片上，而不需要片外滤波器。
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Patent Agency Ranking
公开(公告)号：US08638174B2
公开(公告)日：2014-01-28
申请号：US13116967
申请日：2011-05-26
Applicant: Nenad Pavlovic , Johannes Hubertus Antonius Brekelmans , Jan van Sinderen
CPC classification number: G06F1/025
Abstract: The invention relates to a digital signal generator for providing one or more phases of a local oscillator signal for use in digital to analogue converters and harmonic rejection mixers. Embodiments disclosed include a local oscillator signal generator (200) for a mixer of a radiofrequency receiver, the signal generator (200) comprising a bit sequence generator (201) having a plurality of parallel output lines (203), a digital signal generator (202) having a serial output line (204) and a plurality of input lines connected to respective output lines (203) of the bit sequence generator (201) and a clock signal input line (205), wherein the digital signal generator (202) is configured to provide an output bit sequence on the serial output line (204) at a rate given by a clock signal provided on the clock signal input line (205) and a sequence given by a sequence of bits from the bit sequence generator (201) on the plurality of input lines (203).
Abstract translation: 本发明涉及用于提供用于数模转换器和谐波抑制混频器的本地振荡器信号的一个或多个相位的数字信号发生器。 所公开的实施例包括用于射频接收机的混频器的本地振荡器信号发生器（200），所述信号发生器（200）包括具有多个并行输出线（203）的位序发生器（201），数字信号发生器 ）和连接到位序发生器（201）的相应输出线（203）的多条输入线和时钟信号输入线（205），其中数字信号发生器（202）是 被配置为以由在时钟信号输入线（205）上提供的时钟信号给出的速率和由位序列发生器（201）的位序列给出的序列在串行输出线（204）上提供输出比特序列， 在多个输入线（203）上。
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公开(公告)号：US08633780B2
公开(公告)日：2014-01-21
申请号：US13401056
申请日：2012-02-21
Applicant: Kesatoshi Takeuchi
Inventor： Kesatoshi Takeuchi
Abstract: The PWM control circuit is provided. The PWM control circuit includes: a PWM control signal generator that generates a PWM period signal defining a period of a PWM signal and a PWM resolution signal specifying a resolution in one period of the PWM period signal; and a PWM unit that generates the PWM signal based on the PWM period signal and the PWM resolution signal, wherein the PWM control signal generator changes a frequency of the PWM resolution signal while keeping a frequency of the PWM period signal unchanged.
Abstract translation: 提供PWM控制电路。 PWM控制电路包括：PWM控制信号发生器，其在PWM周期信号的一个周期中产生定义PWM信号周期的PWM周期信号和指定分辨率的PWM分辨率信号; 以及PWM单元，其基于PWM周期信号和PWM分辨率信号生成PWM信号，其中PWM控制信号发生器在保持PWM周期信号的频率不变的同时改变PWM分辨率信号的频率。
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8.发明授权公开(公告)号：US08350636B2
公开(公告)日：2013-01-08
申请号：US12419969
申请日：2009-04-07
Applicant: Peter Trattler , Franz Stelzl
Inventor： Peter Trattler , Franz Stelzl
IPC: H03K7/08
Abstract: A modulation arrangement comprises an input (E) for supplying a data signal (DS), a pre-modulator (VMod) that is coupled to the input (E) and features a clock pulse input (TEV) for supplying a pre-clock pulse (VT), a main modulator (HMod) that is coupled to the pre-modulator (VMod) on the input side and comprises a clock pulse input (TEH) for supplying a main clock pulse (HT), as well as an output for providing a modulated control signal (ST), and a switchable current source (Q, S) for providing a current (IS) that is controlled by the modulated control signal (ST) at an output (A) of the modulation arrangement. Furthermore, a method for providing a modulated control signal is disclosed.
Abstract translation: 调制装置包括用于提供数据信号（DS）的输入（E），耦合到输入（E）的预调制器（VMod），并且具有用于提供前置时钟脉冲的时钟脉冲输入（TEV） （VT），主调制器（HMod），其耦合到输入侧的预调制器（VMod），并且包括用于提供主时钟脉冲（HT）的时钟脉冲输入（TEH）以及用于提供主时钟脉冲 提供调制控制信号（ST）和用于提供在调制装置的输出（A）处由调制控制信号（ST）控制的电流（IS）的可切换电流源（Q，S）。 此外，公开了一种提供调制控制信号的方法。
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公开(公告)号：US08279917B2
公开(公告)日：2012-10-02
申请号：US12453606
申请日：2009-05-15
Applicant: Hideyuki Takahashi
Inventor： Hideyuki Takahashi
IPC: H03K7/08
Abstract: A pulse width modulation (PWM) controller includes: a first counter for counting a reference clock signal, and thus outputting a first count value, a leading edge control signal generator for outputting a leading edge control signal on a basis of the first count value, an adjustment clock generator for generating an adjustment clock signal, a second counter controller for instructing the adjustment clock generator to start to output the adjustment clock signal, a second counter for outputting a second count value, a trailing edge control signal generator for outputting a trailing edge control signal on a basis of the second count value, and a PWM pulse generator for synthesizing the leading edge control signal and the trailing edge control signal, and thus generating a pulse width modulation signal.
Abstract translation: 脉冲宽度调制（PWM）控制器包括：第一计数器，用于对参考时钟信号进行计数，从而输出第一计数值;前沿控制信号发生器，用于根据第一计数值输出前沿控制信号; 用于产生调整时钟信号的调整时钟发生器，用于指示调节时钟发生器开始输出调节时钟信号的第二计数器控制器，用于输出第二计数值的第二计数器，用于输出尾随的后沿控制信号发生器 基于第二计数值的边沿控制信号，以及用于合成前沿控制信号和后沿控制信号的PWM脉冲发生器，从而产生脉宽调制信号。
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10.发明申请Systems and methods for precise generation of phase variation in digital signals 有权用于精确生成数字信号相位变化的系统和方法公开(公告)号：US20120176174A1
公开(公告)日：2012-07-12
申请号：US12930490
申请日：2011-01-07
Applicant: Charles A. Webb, III
Inventor： Charles A. Webb, III
IPC: H03K3/00
CPC classification number: G06F1/025 , G06F1/0321
Abstract: Systems and methods are disclosed for precise generation of phase variation in digital signals. The disclosed signal generation embodiments generate a pattern of information bits that represents a digital signal with desired phase variations and transmit this digital pattern at high speed utilizing a serializer to generate a high speed bit stream. The high speed bit stream can be used to generate one or more digital signals, such as clock signals, having desired rates and desired phase variations. In certain embodiments, the desired phase variation can be introduced into the resulting digital signal by removing and/or inserting bits in a digital pattern thereby moving logic transitions (e.g., rising edge transitions, falling edge transitions) as desired within the resulting digital signal. In addition to clock signals, the resulting digital signals generated can be control signals, data signals and/or any other desired digital signal.
Abstract translation: 公开了用于在数字信号中精确地产生相位变化的系统和方法。 所公开的信号生成实施例产生表示具有期望的相位变化的数字信号的信息比特的模式，并且利用串行器高速地传送该数字模式以生成高速比特流。 高速比特流可用于产生具有期望速率和期望相位变化的一个或多个数字信号，例如时钟信号。 在某些实施例中，可以通过去除和/或插入数字图形中的位来将期望的相位变化引入到所得数字信号中，从而根据期望在所得到的数字信号中移动逻辑转换（例如，上升沿转变，下降沿转换）。 除了时钟信号之外，所生成的数字信号可以是控制信号，数据信号和/或任何其它所需的数字信号。
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