公开(公告)号：US07750685B1

公开(公告)日：2010-07-06

申请号：US12251757

申请日：2008-10-15

申请人： Ryan Bunch ,  Stephen T. Janesch

发明人： Ryan Bunch ,  Stephen T. Janesch

IPC分类号： H03K9/06 ,  H03D3/00

CPC分类号： H03L7/087 ,  H03L7/099 ,  H03L7/10 ,  H03L7/18 ,  H03L2207/12

摘要： A first embodiment of the present invention relates to a frequency and phase locked loop (FPLL) synthesizer having a frequency-locked loop (FLL) operating mode and a phase-locked loop (PLL) operating mode. The FLL operating mode is used for rapid coarse tuning of the FPLL synthesizer and is followed by the PLL operating mode for fine tuning and stabilization of the frequency of an output signal from the FPLL synthesizer. A second embodiment of the present invention relates to a high resolution frequency measurement circuit that is capable of directly measuring the frequency of a high frequency signal to provide a high resolution frequency measurement using a lower frequency reference signal, and may include linear feedback shift register (LFSR) circuitry and LFSR-to-binary conversion circuitry. A third embodiment of the present invention relates to an FPLL having an FLL that includes the high resolution frequency measurement circuit.

摘要翻译： 本发明的第一实施例涉及具有锁相环（FLL）操作模式和锁相环（PLL）操作模式的频率和锁相环（FPLL）合成器。 FLL操作模式用于FPLL合成器的快速粗调，后跟PLL操作模式，用于微调和稳定来自FPLL合成器的输出信号的频率。 本发明的第二实施例涉及一种高分辨率频率测量电路，其能够直接测量高频信号的频率以使用较低频率参考信号提供高分辨率频率测量，并且可以包括线性反馈移位寄存器 LFSR）电路和LFSR至二进制转换电路。 本发明的第三实施例涉及一种具有包括高分辨率频率测量电路的FLL的FPLL。

公开(公告)号：US07023282B1

公开(公告)日：2006-04-04

申请号：US10901546

申请日：2004-07-29

申请人： Scott Humpreys ,  Ryan Bunch

发明人： Scott Humpreys ,  Ryan Bunch

IPC分类号： H03L7/10 ,  H03L7/18

CPC分类号： H03L7/18 ,  H03J2200/10 ,  H03L7/113 ,  H03L7/1976 ,  H03L7/199

摘要： An improved coarse tuning process for fractional-N frequency synthesizers is provided. In general, a coarse tuning circuit controls a phase lock loop (PLL) of a frequency synthesizer. During coarse tuning, a reference signal used to control an output frequency of the PLL is provided to the coarse tuning circuitry and is divided by a factor M to provide a divided reference signal. A controllable oscillator (CO) output signal from a CO in the PLL is divided by an N divider in the PLL to provide a divided CO signal. The periods or, equivalently, frequencies of the divided CO signal and the divided reference signal are compared, and the result is used to select an appropriate tuning curve for the CO. In order to reduce a period comparison error, synchronization circuitry operates to synchronize the N divider of the PLL and an M divider of the coarse tuning circuit.

摘要翻译： 提供了一种用于分数N频率合成器的改进的粗调程序。 通常，粗调电路控制频率合成器的锁相环（PLL）。 在粗调时，用于控制PLL的输出频率的参考信号被提供给粗调电路，并被因子M除以提供分频参考信号。 来自PLL中的CO的可控振荡器（CO）输出信号被PLL中的N分频器除以提供分频的CO信号。 比较分频CO信号和分频参考信号的周期或等效的频率，结果用于选择CO的适当调谐曲线。为了减少周期比较误差，同步电路用于同步 PLL的分频器和粗调谐电路的M分频器。

公开(公告)号：US20060170505A1

公开(公告)日：2006-08-03

申请号：US11047258

申请日：2005-01-31

申请人： Scott Humphreys ,  Ryan Bunch ,  Barry Hunt ,  Alexander Wayne Hietala

发明人： Scott Humphreys ,  Ryan Bunch ,  Barry Hunt ,  Alexander Wayne Hietala

IPC分类号： H03L7/00

CPC分类号： H03L7/1976 ,  H03C3/0966 ,  H03L7/23 ,  H03L2207/12

摘要： A fractional-N offset phase locked loop (FN-OPLL) is provided. The FN-OPLL includes a fractional divider, a phase detector, a loop filter, a voltage controlled oscillator (VCO), and feedback circuitry. Combiner circuitry combines an initial fractional divide value and a modulation signal to provide a combined fractional divide value. Based on the combined fractional divide value, the fractional-N divider divides a reference frequency and provides a divided reference frequency to the phase detector. The phase detector compares a phase of the divided reference frequency to a phase of a feedback signal to provide a comparison signal. The comparison signal is filtered by the loop filter to provide a control signal to the VCO, where the control signal controls a frequency of an output signal of the VCO. The output signal is processed by the feedback circuitry to provide the feedback signal to the phase detector.

摘要翻译： 提供了一个分数N偏移锁相环（FN-OPLL）。 FN-OPLL包括分数分频器，相位检测器，环路滤波器，压控振荡器（VCO）和反馈电路。 组合器电路组合初始分数除法值和调制信号以提供组合分数除数值。 基于组合分数除法，分数N分频器划分参考频率，并向相位检测器提供分频参考频率。 相位检测器将分频参考频率的相位与反馈信号的相位进行比较，以提供比较信号。 比较信号由环路滤波器滤波，以向VCO提供控制信号，其中控制信号控制VCO的输出信号的频率。 输出信号由反馈电路处理，以将反馈信号提供给相位检测器。

公开(公告)号：US07274229B1

公开(公告)日：2007-09-25

申请号：US11472889

申请日：2006-06-22

申请人： Scott Humphreys ,  Ryan Bunch

发明人： Scott Humphreys ,  Ryan Bunch

IPC分类号： H03L7/06

CPC分类号： H03L7/10 ,  H03J2200/10 ,  H03L7/193 ,  H03L7/1974

摘要： An improved coarse tuning process for fractional-N frequency synthesizers is provided. In general, a coarse tuning circuit controls a phase lock loop (PLL) of a frequency synthesizer such that the phase lock loop operates in an integer division mode during coarse tuning, thereby eliminating jitter due to fractional-N operation during coarse tuning. The coarse tuning circuit includes divide value generation circuitry that provides an integer divide value to an N divider of the PLL during coarse tuning and a fractional-N sequence to the N divider during fractional-N operation.

摘要翻译： 提供了一种用于分数N频率合成器的改进的粗调程序。 通常，粗调电路控制频率合成器的锁相环（PLL），使得在粗调谐期间锁相环以整数分频模式工作，从而消除了在粗调谐期间由于分数-N运算引起的抖动。 粗调电路包括分频值产生电路，其在粗调谐期间向PLL的N分频器提供整数分频值，并且在小数N运算期间向N分频器提供分数N序列。

公开(公告)号：US20060197613A1

公开(公告)日：2006-09-07

申请号：US11415808

申请日：2006-05-02

申请人： Ryan Bunch ,  Alexander Hietala ,  Scott Humphreys

发明人： Ryan Bunch ,  Alexander Hietala ,  Scott Humphreys

IPC分类号： H03L7/00

CPC分类号： H03L7/1976 ,  H03C3/0966 ,  H03L7/23 ,  H03L2207/12

摘要： A linearization system is provided for a Fractional-N Offset Phase Locked Loop (FN-OPLL) in a frequency or phase modulation system. In general, the linearization system processes a modulation signal to provide a linearized modulation signal to a fractional-N divider in a reference path of the FN-OPLL such that a frequency or phase modulation component at the output of the FN-OPLL is substantially linear with respect to the modulation signal.

摘要翻译： 在频率或相位调制系统中为分数N偏移锁相环（FN-OPLL）提供线性化系统。 通常，线性化系统处理调制信号以向FN-OPLL的参考路径中的分数N分频器提供线性调制信号，使得FN-OPLL的输出处的频率或相位调制分量基本上是线性的 相对于调制信号。

公开(公告)号：US07064591B1

公开(公告)日：2006-06-20

申请号：US10901669

申请日：2004-07-29

申请人： Scott Humphreys ,  Ryan Bunch

发明人： Scott Humphreys ,  Ryan Bunch

IPC分类号： H03L7/06

CPC分类号： H03L7/10 ,  H03J2200/10 ,  H03L7/193 ,  H03L7/1974

摘要： An improved coarse tuning process for fractional-N frequency synthesizers is provided. In general, a coarse tuning circuit controls a phase lock loop (PLL) of a frequency synthesizer such that the phase lock loop operates in an integer division mode during coarse tuning, thereby eliminating jitter due to fractional-N operation during coarse tuning. The coarse tuning circuit includes divide value generation circuitry that provides an integer divide value to an N divider of the PLL during coarse tuning and a fractional-N sequence to the N divider during fractional-N operation.

摘要翻译： 提供了一种用于分数N频率合成器的改进的粗调程序。 通常，粗调电路控制频率合成器的锁相环（PLL），使得在粗调谐期间锁相环以整数分频模式工作，从而消除了在粗调谐期间由于分数-N运算引起的抖动。 粗调电路包括分频值产生电路，其在粗调谐期间向PLL的N分频器提供整数分频值，并且在小数N运算期间向N分频器提供分数N序列。