发明授权
- 专利标题: Frequency-locked loop calibration of a phase-locked loop gain
- 专利标题(中): 锁相环增益的锁相环校准
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申请号: US12341638申请日: 2008-12-22
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公开(公告)号: US07898343B1公开(公告)日: 2011-03-01
- 发明人: Stephen T. Janesch
- 申请人: Stephen T. Janesch
- 申请人地址: US NC Greensboro
- 专利权人: RF Micro Devices, Inc.
- 当前专利权人: RF Micro Devices, Inc.
- 当前专利权人地址: US NC Greensboro
- 代理机构: Withrow & Terranova, P.L.L.C.
- 主分类号: H03L7/00
- IPC分类号: H03L7/00
摘要:
The present invention relates to a calibrated phase-locked loop (PLL), which has a calibration mode for measuring a tuning gain of a variable frequency oscillator (VFO) and a PLL mode for normal operation. Calibration information based on the tuning gain is used during the PLL mode to regulate a PLL loop gain. During the calibration mode, the calibrated PLL operates as a frequency-locked loop (FLL) for low frequency lock times, and during the PLL mode the calibrated PLL operates as a PLL for high frequency accuracy and low noise. By regulating the PLL loop gain, the desired noise spectrum and dynamic behavior of the PLL may be maintained in spite of variations in the operating characteristics or in the characteristics of the PLL components.
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