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1.发明申请SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF AND SUBSTRATE AND PACKAGING STRUCTURE 审中-公开半导体封装及其制造方法及其基板和封装结构公开(公告)号：US20150123287A1
公开(公告)日：2015-05-07
申请号：US14133868
申请日：2013-12-19
Applicant: Siliconware Precision Industries Co., Ltd
Inventor： Chu-Chi Hsu , Lung-Yuan Wang , Cheng-Chia Chiang , Chia-Kai Shih
CPC classification number: H01L21/02057 , H01L21/561 , H01L21/563 , H01L21/568 , H01L23/13 , H01L23/49816 , H01L23/49833 , H01L23/562 , H01L24/16 , H01L24/32 , H01L24/48 , H01L24/73 , H01L24/81 , H01L24/83 , H01L24/85 , H01L24/97 , H01L25/0655 , H01L25/105 , H01L25/50 , H01L2224/16225 , H01L2224/32225 , H01L2224/48227 , H01L2224/73204 , H01L2224/81005 , H01L2224/83005 , H01L2224/85005 , H01L2224/97 , H01L2225/1023 , H01L2225/1058 , H01L2924/00014 , H01L2924/15162 , H01L2924/15174 , H01L2924/15331 , H01L2924/181 , H01L2924/3511 , Y10T428/192 , H01L2224/83 , H01L2224/81 , H01L2224/85 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
Abstract: A method for fabricating a semiconductor package is disclosed, which includes the steps of: providing a first substrate; disposing a second substrate on the first substrate through a plurality of supporting elements, wherein the second substrate has at least a cleaning hole penetrating therethrough; and performing a cleaning process to clean space between the second substrate and the first substrate through the cleaning hole, thereby preventing a popcorn effect from occurring when the first substrate is heated and hence preventing delamination of the semiconductor package. Further, the cleaning hole facilitates to disperse thermal stresses so as to prevent warping of the first and second substrates during a chip-bonding or encapsulating process, thereby overcoming the conventional drawbacks of cracking of the supporting elements and a short circuit therebetween.
Abstract translation: 公开了一种制造半导体封装的方法，其包括以下步骤：提供第一衬底; 通过多个支撑元件将第二基板设置在第一基板上，其中第二基板至少具有贯穿其中的清洁孔; 并且通过清洁孔进行清洁处理以清洁第二基板和第一基板之间的空间，从而防止当第一基板被加热时出现爆米花效应，从而防止半导体封装的分层。 此外，清洁孔有利于分散热应力，以防止在芯片接合或封装过程中第一和第二基板的翘曲，从而克服了支撑元件的破裂和它们之间的短路的常规缺点。
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公开(公告)号：US20150255360A1
公开(公告)日：2015-09-10
申请号：US14452871
申请日：2014-08-06
Applicant: Siliconware Precision Industries Co., Ltd.
Inventor： Chu-Chi Hsu , Lung-Yuan Wang , Cheng-Chia Chiang , Chia-Kai Shih , Shu-Huei Huang
CPC classification number: H01L23/3128 , H01L23/49811 , H01L23/49816 , H01L24/13 , H01L24/16 , H01L24/32 , H01L24/73 , H01L24/81 , H01L24/92 , H01L25/0657 , H01L25/105 , H01L25/16 , H01L25/50 , H01L2224/0401 , H01L2224/131 , H01L2224/13147 , H01L2224/13186 , H01L2224/16168 , H01L2224/16225 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73204 , H01L2224/73265 , H01L2224/92125 , H01L2225/06517 , H01L2225/1017 , H01L2225/1023 , H01L2225/1041 , H01L2225/1058 , H01L2924/15311 , H01L2924/15331 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19102 , H01L2924/19103 , H01L2924/3511 , H01L2924/37001 , H01L2924/014 , H01L2924/00 , H01L2924/00014
Abstract: A package on package (PoP) structure is provided, which includes: a packaging substrate having a plurality of conductive bumps, wherein each of the conductive bumps has a metal ball and a solder material covering the metal ball; and an electronic element having a plurality of conductive posts, wherein the electronic element is stacked on the packaging substrate by correspondingly bonding the conductive posts to the conductive bumps, and each of the conductive posts and the corresponding conductive bump form a conductive element. The present invention facilitates the stacking process through butt joint of the conductive posts and the metal balls of the conductive bumps.
Abstract translation: 提供一种封装封装（PoP）结构，其包括：具有多个导电凸块的封装基板，其中每个导电凸块具有覆盖金属球的金属球和焊料; 以及具有多个导电柱的电子元件，其中通过将导电柱相应地接合到导电凸块上，电子元件堆叠在封装衬底上，并且每个导电柱和相应的导电凸块形成导电元件。 本发明有助于通过导电柱和导电凸块的金属球的对接的堆叠过程。
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公开(公告)号：US09343387B2
公开(公告)日：2016-05-17
申请号：US14452871
申请日：2014-08-06
Applicant: Siliconware Precision Industries Co., Ltd.
Inventor： Chu-Chi Hsu , Lung-Yuan Wang , Cheng-Chia Chiang , Chia-Kai Shih , Shu-Huei Huang
IPC: H01L23/31 , H01L25/10 , H01L23/498 , H01L25/065 , H01L25/00 , H01L23/00 , H01L25/16
CPC classification number: H01L23/3128 , H01L23/49811 , H01L23/49816 , H01L24/13 , H01L24/16 , H01L24/32 , H01L24/73 , H01L24/81 , H01L24/92 , H01L25/0657 , H01L25/105 , H01L25/16 , H01L25/50 , H01L2224/0401 , H01L2224/131 , H01L2224/13147 , H01L2224/13186 , H01L2224/16168 , H01L2224/16225 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73204 , H01L2224/73265 , H01L2224/92125 , H01L2225/06517 , H01L2225/1017 , H01L2225/1023 , H01L2225/1041 , H01L2225/1058 , H01L2924/15311 , H01L2924/15331 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19102 , H01L2924/19103 , H01L2924/3511 , H01L2924/37001 , H01L2924/014 , H01L2924/00 , H01L2924/00014
Abstract: A package on package (PoP) structure is provided, which includes: a packaging substrate having a plurality of conductive bumps, wherein each of the conductive bumps has a metal ball and a solder material covering the metal ball; and an electronic element having a plurality of conductive posts, wherein the electronic element is stacked on the packaging substrate by correspondingly bonding the conductive posts to the conductive bumps, and each of the conductive posts and the corresponding conductive bump form a conductive element. The present invention facilitates the stacking process through butt joint of the conductive posts and the metal balls of the conductive bumps.
Abstract translation: 提供一种封装封装（PoP）结构，其包括：具有多个导电凸块的封装基板，其中每个导电凸块具有覆盖金属球的金属球和焊料; 以及具有多个导电柱的电子元件，其中通过将导电柱相应地接合到导电凸块上，电子元件堆叠在封装衬底上，并且每个导电柱和相应的导电凸块形成导电元件。 本发明有助于通过导电柱和导电凸块的金属球的对接的堆叠过程。
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Patent Agency Ranking
公开(公告)号：US09356008B2
公开(公告)日：2016-05-31
申请号：US14616013
申请日：2015-02-06
Applicant: Siliconware Precision Industries Co., Ltd.
Inventor： Cheng-Chia Chiang , Hsin-Ta Lin , Fu-Tang Huang , Yu-Po Wang , Lung-Yuan Wang , Chu-Chi Hsu , Chia-Kai Shih
CPC classification number: H01L25/162 , H01L23/3128 , H01L23/3157 , H01L23/42 , H01L23/49816 , H01L23/49833 , H01L23/562 , H01L23/564 , H01L24/05 , H01L24/06 , H01L24/11 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/17 , H01L24/29 , H01L24/32 , H01L24/81 , H01L24/83 , H01L25/0657 , H01L25/105 , H01L25/50 , H01L2224/0401 , H01L2224/05015 , H01L2224/05016 , H01L2224/05078 , H01L2224/0519 , H01L2224/05561 , H01L2224/05582 , H01L2224/056 , H01L2224/05611 , H01L2224/06132 , H01L2224/06181 , H01L2224/11825 , H01L2224/12105 , H01L2224/13014 , H01L2224/13017 , H01L2224/13023 , H01L2224/13078 , H01L2224/13082 , H01L2224/13083 , H01L2224/13111 , H01L2224/13144 , H01L2224/13147 , H01L2224/1319 , H01L2224/13582 , H01L2224/13671 , H01L2224/1369 , H01L2224/1401 , H01L2224/141 , H01L2224/16145 , H01L2224/16147 , H01L2224/16227 , H01L2224/16237 , H01L2224/1703 , H01L2224/17051 , H01L2224/17181 , H01L2224/17517 , H01L2224/17519 , H01L2224/291 , H01L2224/2929 , H01L2224/293 , H01L2224/32145 , H01L2224/32225 , H01L2224/73204 , H01L2224/73253 , H01L2224/81191 , H01L2224/81192 , H01L2224/81193 , H01L2224/81815 , H01L2224/83101 , H01L2224/83801 , H01L2224/8385 , H01L2225/06513 , H01L2225/06548 , H01L2225/06568 , H01L2225/1023 , H01L2225/1058 , H01L2225/1082 , H01L2924/0635 , H01L2924/15311 , H01L2924/15321 , H01L2924/15331 , H01L2924/18161 , H01L2924/381 , H01L2924/3841 , H01L2924/00012 , H01L2924/00014 , H01L2924/01082 , H01L2924/01047 , H01L2924/01029 , H01L2924/07025 , H01L2924/00
Abstract: A semiconductor package is provided, which includes: a first semiconductor device having a first top surface and a first bottom surface opposite to the first top surface; a plurality of conductive balls formed on the first top surface of the first semiconductor device; a second semiconductor device having a second top surface and a second bottom surface opposite to the second top surface; and a plurality of conductive posts formed on the second bottom surface of the second semiconductor device and correspondingly bonded to the conductive balls for electrically connecting the first semiconductor device and the second semiconductor device, wherein the conductive posts have a height less than 300 um. Therefore, the present invention can easily control the height of the semiconductor package and is applicable to semiconductor packages having fine-pitch conductive balls.
Abstract translation: 提供一种半导体封装，其包括：第一半导体器件，其具有第一顶表面和与第一顶表面相对的第一底表面; 形成在所述第一半导体器件的所述第一顶表面上的多个导电球; 具有第二顶表面和与第二顶表面相对的第二底表面的第二半导体器件; 以及形成在所述第二半导体器件的所述第二底表面上并相应地接合到所述导电球以用于电连接所述第一半导体器件和所述第二半导体器件的多个导电柱，其中所述导电柱的高度小于300μm。 因此，本发明可以容易地控制半导体封装的高度，并且可应用于具有细间距导电球的半导体封装。
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公开(公告)号：US09343421B2
公开(公告)日：2016-05-17
申请号：US14309119
申请日：2014-06-19
Applicant: Siliconware Precision Industries Co., Ltd.
Inventor： Lung-Yuan Wang , Cheng-Chia Chiang , Chu-Chi Hsu , Chia-Kai Shih , Shu-Huei Huang
IPC: H01L33/00 , H01L23/00 , H01L21/56 , H01L25/10 , H01L25/00 , H01L23/31 , H01L23/498 , H01L23/538
CPC classification number: H01L25/50 , H01L21/568 , H01L23/3128 , H01L23/49811 , H01L23/5389 , H01L24/03 , H01L24/19 , H01L24/73 , H01L24/96 , H01L25/105 , H01L2224/0231 , H01L2224/02331 , H01L2224/04105 , H01L2224/12105 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73204 , H01L2224/73265 , H01L2225/0651 , H01L2225/06548 , H01L2225/06562 , H01L2225/1023 , H01L2225/1035 , H01L2225/1041 , H01L2225/1058 , H01L2924/00014 , H01L2924/15311 , H01L2924/181 , H01L2924/00012 , H01L2224/45099 , H01L2224/29099 , H01L2224/13099 , H01L2924/00
Abstract: A method for fabricating a semiconductor package is provided, which includes the steps of: providing a first substrate having a plurality of first conductive posts on a surface thereof and providing a second substrate having a third surface having a chip disposed thereon and a fourth surface opposite to the third surface; disposing the first substrate on the third surface of the second substrate through the first conductive posts; forming an encapsulant between the first substrate and the second substrate, wherein the encapsulant has a first surface adjacent to the first substrate and a second surface opposite to the first surface; and removing the first substrate, thereby effectively preventing solder bridging from occurring.
Abstract translation: 提供一种制造半导体封装的方法，其包括以下步骤：提供在其表面上具有多个第一导电柱的第一衬底，并提供第二衬底，该第二衬底具有设置在其上的芯片的第三表面和与其相对的第四表面 到第三面; 通过第一导电柱将第一衬底设置在第二衬底的第三表面上; 在所述第一基板和所述第二基板之间形成密封剂，其中所述密封剂具有与所述第一基板相邻的第一表面和与所述第一表面相对的第二表面; 并移除第一基板，从而有效地防止焊料桥接发生。
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公开(公告)号：US20150200169A1
公开(公告)日：2015-07-16
申请号：US14309119
申请日：2014-06-19
Applicant: Siliconware Precision Industries Co., Ltd.
Inventor： Lung-Yuan Wang , Cheng-Chia Chiang , Chu-Chi Hsu , Chia-Kai Shih , Shu-Huei Huang
CPC classification number: H01L25/50 , H01L21/568 , H01L23/3128 , H01L23/49811 , H01L23/5389 , H01L24/03 , H01L24/19 , H01L24/73 , H01L24/96 , H01L25/105 , H01L2224/0231 , H01L2224/02331 , H01L2224/04105 , H01L2224/12105 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73204 , H01L2224/73265 , H01L2225/0651 , H01L2225/06548 , H01L2225/06562 , H01L2225/1023 , H01L2225/1035 , H01L2225/1041 , H01L2225/1058 , H01L2924/00014 , H01L2924/15311 , H01L2924/181 , H01L2924/00012 , H01L2224/45099 , H01L2224/29099 , H01L2224/13099 , H01L2924/00
Abstract: A method for fabricating a semiconductor package is provided, which includes the steps of: providing a first substrate having a plurality of first conductive posts on a surface thereof and providing a second substrate having a third surface having a chip disposed thereon and a fourth surface opposite to the third surface; disposing the first substrate on the third surface of the second substrate through the first conductive posts; forming an encapsulant between the first substrate and the second substrate, wherein the encapsulant has a first surface adjacent to the first substrate and a second surface opposite to the first surface; and removing the first substrate, thereby effectively preventing solder bridging from occurring.
Abstract translation: 提供一种制造半导体封装的方法，其包括以下步骤：提供在其表面上具有多个第一导电柱的第一衬底，并提供第二衬底，该第二衬底具有设置在其上的芯片的第三表面和与其相对的第四表面 到第三面; 通过第一导电柱将第一衬底设置在第二衬底的第三表面上; 在所述第一基板和所述第二基板之间形成密封剂，其中所述密封剂具有与所述第一基板相邻的第一表面和与所述第一表面相对的第二表面; 并移除第一基板，从而有效地防止焊料桥接发生。
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公开(公告)号：US20160233205A1
公开(公告)日：2016-08-11
申请号：US15134037
申请日：2016-04-20
Applicant: Siliconware Precision Industries Co., Ltd.
Inventor： Lung-Yuan Wang , Cheng-Chia Chiang , Chu-Chi Hsu , Chia-Kai Shih , Shu-Huei Huang
CPC classification number: H01L25/50 , H01L21/568 , H01L23/3128 , H01L23/49811 , H01L23/5389 , H01L24/03 , H01L24/19 , H01L24/73 , H01L24/96 , H01L25/105 , H01L2224/0231 , H01L2224/02331 , H01L2224/04105 , H01L2224/12105 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73204 , H01L2224/73265 , H01L2225/0651 , H01L2225/06548 , H01L2225/06562 , H01L2225/1023 , H01L2225/1035 , H01L2225/1041 , H01L2225/1058 , H01L2924/00014 , H01L2924/15311 , H01L2924/181 , H01L2924/00012 , H01L2224/45099 , H01L2224/29099 , H01L2224/13099 , H01L2924/00
Abstract: A method for fabricating a semiconductor package is provided, which includes the steps of: providing a first substrate having a plurality of first conductive posts on a surface thereof and providing a second substrate having a third surface having a chip disposed thereon and a fourth surface opposite to the third surface; disposing the first substrate on the third surface of the second substrate through the first conductive posts; forming an encapsulant between the first substrate and the second substrate, wherein the encapsulant has a first surface adjacent to the first substrate and a second surface opposite to the first surface; and removing the first substrate, thereby effectively preventing solder bridging from occurring.
Abstract translation: 提供一种制造半导体封装的方法，其包括以下步骤：提供在其表面上具有多个第一导电柱的第一衬底，并提供第二衬底，该第二衬底具有设置在其上的芯片的第三表面和与其相对的第四表面 到第三面; 通过第一导电柱将第一衬底设置在第二衬底的第三表面上; 在所述第一基板和所述第二基板之间形成密封剂，其中所述密封剂具有与所述第一基板相邻的第一表面和与所述第一表面相对的第二表面; 并移除第一基板，从而有效地防止焊料桥接发生。
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公开(公告)号：US20150041972A1
公开(公告)日：2015-02-12
申请号：US14249626
申请日：2014-04-10
Applicant: Siliconware Precision Industries Co., Ltd.
Inventor： Chia-Kai Shih , Lung-Yuan Wang , Cheng-Chia Chiang , Chu-Chi Hsu , Shih-Hao Tung
IPC: H01L25/065 , H01L23/00
CPC classification number: H01L24/97 , H01L23/49811 , H01L23/49833 , H01L23/5389 , H01L24/73 , H01L24/81 , H01L24/83 , H01L24/92 , H01L25/105 , H01L25/50 , H01L2224/16237 , H01L2224/2919 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73253 , H01L2224/73265 , H01L2224/83191 , H01L2224/92225 , H01L2224/97 , H01L2225/1023 , H01L2225/1041 , H01L2225/1058 , H01L2924/15311 , H01L2924/15331 , H01L2924/181 , H01L2224/81 , H01L2224/83 , H01L2924/00012 , H01L2924/00 , H01L2924/00014
Abstract: A semiconductor package is disclosed, which includes: a first substrate; a first semiconductor component disposed on the first substrate; a second substrate disposed on the first semiconductor component and electrically connected to the first substrate through a plurality of conductive elements; and a first encapsulant formed between the first substrate and the second substrate and encapsulating the first semiconductor component and the conductive elements. The present invention can control the height and volume of the conductive elements since the distance between the first substrate and the second substrate is fixed by bonding the second substrate to the first semiconductor component.
Abstract translation: 公开了一种半导体封装，其包括：第一衬底; 设置在所述第一基板上的第一半导体部件; 第二基板，设置在所述第一半导体部件上，并且通过多个导电元件电连接到所述第一基板; 以及形成在第一基板和第二基板之间并封装第一半导体部件和导电元件的第一密封剂。 本发明可以控制导电元件的高度和体积，因为通过将第二基板结合到第一半导体部件来固定第一基板和第二基板之间的距离。
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