公开(公告)号：US20170207104A1

公开(公告)日：2017-07-20

申请号：US15478508

申请日：2017-04-04

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Cheng-Chia Chiang ,  Don-Son Jiang ,  Lung-Yuan Wang ,  Shih-Hao Tung ,  Shu-Huei Huang

IPC: H01L21/56 ,  H01L23/00 ,  H01L23/498 ,  H01L23/538 ,  H01L21/48 ,  H01L23/31

CPC classification number: H01L21/563 ,  H01L21/4853 ,  H01L21/486 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05568 ,  H01L2224/05647 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81815 ,  H01L2224/92125 ,  H01L2924/14 ,  H01L2924/18161 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/014

Abstract: A semiconductor package is provided, which includes: a packaging substrate having opposite first and second surfaces and a plurality of first and second conductive pads formed on the first surface; a chip having opposite active and inactive surfaces and disposed on the first conductive pads via the active surface thereof; a plurality of conductive posts formed on the second conductive pads, respectively; and a first encapsulant formed on the first surface of the packaging substrate for encapsulating the chip and the conductive posts and having a plurality of openings for exposing upper surfaces of the conductive posts, thereby increasing the package density and protecting the chip and the interconnection structure from being adversely affected by intrusion of moisture.

公开(公告)号：US20150255360A1

公开(公告)日：2015-09-10

申请号：US14452871

申请日：2014-08-06

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chu-Chi Hsu ,  Lung-Yuan Wang ,  Cheng-Chia Chiang ,  Chia-Kai Shih ,  Shu-Huei Huang

IPC: H01L23/31 ,  H01L25/10 ,  H01L23/00

CPC classification number: H01L23/3128 ,  H01L23/49811 ,  H01L23/49816 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/16 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13186 ,  H01L2224/16168 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/92125 ,  H01L2225/06517 ,  H01L2225/1017 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19102 ,  H01L2924/19103 ,  H01L2924/3511 ,  H01L2924/37001 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A package on package (PoP) structure is provided, which includes: a packaging substrate having a plurality of conductive bumps, wherein each of the conductive bumps has a metal ball and a solder material covering the metal ball; and an electronic element having a plurality of conductive posts, wherein the electronic element is stacked on the packaging substrate by correspondingly bonding the conductive posts to the conductive bumps, and each of the conductive posts and the corresponding conductive bump form a conductive element. The present invention facilitates the stacking process through butt joint of the conductive posts and the metal balls of the conductive bumps.

Abstract translation: 提供一种封装封装（PoP）结构，其包括：具有多个导电凸块的封装基板，其中每个导电凸块具有覆盖金属球的金属球和焊料; 以及具有多个导电柱的电子元件，其中通过将导电柱相应地接合到导电凸块上，电子元件堆叠在封装衬底上，并且每个导电柱和相应的导电凸块形成导电元件。 本发明有助于通过导电柱和导电凸块的金属球的对接的堆叠过程。

公开(公告)号：US20180138158A1

公开(公告)日：2018-05-17

申请号：US15867910

申请日：2018-01-11

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Shih-Hao Tung ,  Chang-Yi Lan ,  Lung-Yuan Wang ,  Cheng-Chia Chiang ,  Shu-Huei Huang

IPC: H01L25/10 ,  H01L25/00 ,  H01L23/31 ,  H01L25/065 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L25/105 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49816 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/131 ,  H01L2224/16237 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/207

Abstract: A method for fabricating a package on package (PoP) structure is provided, which includes: providing a first packaging substrate having at least a first electronic element and a plurality of first support portions, wherein the first electronic element is electrically connected to the first packaging substrate; forming an encapsulant on the first packaging substrate for encapsulating the first electronic element and the first support portions; forming a plurality of openings in the encapsulant for exposing portions of surfaces of the first support portions; and providing a second packaging substrate having a plurality of second support portions and stacking the second packaging substrate on the first packaging substrate with the second support portions positioned in the openings of the encapsulant and bonded with the first support portions. As such, the encapsulant effectively separates the first support portions or the second support portions from one another to prevent bridging from occurring therebetween.

公开(公告)号：US20160233205A1

公开(公告)日：2016-08-11

申请号：US15134037

申请日：2016-04-20

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Lung-Yuan Wang ,  Cheng-Chia Chiang ,  Chu-Chi Hsu ,  Chia-Kai Shih ,  Shu-Huei Huang

IPC: H01L25/00 ,  H01L25/10 ,  H01L23/538 ,  H01L23/00 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L25/50 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/19 ,  H01L24/73 ,  H01L24/96 ,  H01L25/105 ,  H01L2224/0231 ,  H01L2224/02331 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06548 ,  H01L2225/06562 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/29099 ,  H01L2224/13099 ,  H01L2924/00

Abstract: A method for fabricating a semiconductor package is provided, which includes the steps of: providing a first substrate having a plurality of first conductive posts on a surface thereof and providing a second substrate having a third surface having a chip disposed thereon and a fourth surface opposite to the third surface; disposing the first substrate on the third surface of the second substrate through the first conductive posts; forming an encapsulant between the first substrate and the second substrate, wherein the encapsulant has a first surface adjacent to the first substrate and a second surface opposite to the first surface; and removing the first substrate, thereby effectively preventing solder bridging from occurring.

Abstract translation: 提供一种制造半导体封装的方法，其包括以下步骤：提供在其表面上具有多个第一导电柱的第一衬底，并提供第二衬底，该第二衬底具有设置在其上的芯片的第三表面和与其相对的第四表面 到第三面; 通过第一导电柱将第一衬底设置在第二衬底的第三表面上; 在所述第一基板和所述第二基板之间形成密封剂，其中所述密封剂具有与所述第一基板相邻的第一表面和与所述第一表面相对的第二表面; 并移除第一基板，从而有效地防止焊料桥接发生。

公开(公告)号：US09646921B2

公开(公告)日：2017-05-09

申请号：US14255326

申请日：2014-04-17

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Cheng-Chia Chiang ,  Don-Son Jiang ,  Lung-Yuan Wang ,  Shih-Hao Tung ,  Shu-Huei Huang

IPC: H01L23/498 ,  H01L23/31 ,  H01L21/48 ,  H01L23/538 ,  H01L23/00

CPC classification number: H01L21/563 ,  H01L21/4853 ,  H01L21/486 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05568 ,  H01L2224/05647 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81815 ,  H01L2224/92125 ,  H01L2924/14 ,  H01L2924/18161 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/014

Abstract: A semiconductor package is provided, which includes: a packaging substrate having opposite first and second surfaces and a plurality of first and second conductive pads formed on the first surface; a chip having opposite active and inactive surfaces and disposed on the first conductive pads via the active surface thereof; a plurality of conductive posts formed on the second conductive pads, respectively; and a first encapsulant formed on the first surface of the packaging substrate for encapsulating the chip and the conductive posts and having a plurality of openings for exposing upper surfaces of the conductive posts, thereby increasing the package density and protecting the chip and the interconnection structure from being adversely affected by intrusion of moisture.

公开(公告)号：US09343387B2

公开(公告)日：2016-05-17

申请号：US14452871

申请日：2014-08-06

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chu-Chi Hsu ,  Lung-Yuan Wang ,  Cheng-Chia Chiang ,  Chia-Kai Shih ,  Shu-Huei Huang

IPC: H01L23/31 ,  H01L25/10 ,  H01L23/498 ,  H01L25/065 ,  H01L25/00 ,  H01L23/00 ,  H01L25/16

CPC classification number: H01L23/3128 ,  H01L23/49811 ,  H01L23/49816 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/16 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13186 ,  H01L2224/16168 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/92125 ,  H01L2225/06517 ,  H01L2225/1017 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19102 ,  H01L2924/19103 ,  H01L2924/3511 ,  H01L2924/37001 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A package on package (PoP) structure is provided, which includes: a packaging substrate having a plurality of conductive bumps, wherein each of the conductive bumps has a metal ball and a solder material covering the metal ball; and an electronic element having a plurality of conductive posts, wherein the electronic element is stacked on the packaging substrate by correspondingly bonding the conductive posts to the conductive bumps, and each of the conductive posts and the corresponding conductive bump form a conductive element. The present invention facilitates the stacking process through butt joint of the conductive posts and the metal balls of the conductive bumps.

Abstract translation: 提供一种封装封装（PoP）结构，其包括：具有多个导电凸块的封装基板，其中每个导电凸块具有覆盖金属球的金属球和焊料; 以及具有多个导电柱的电子元件，其中通过将导电柱相应地接合到导电凸块上，电子元件堆叠在封装衬底上，并且每个导电柱和相应的导电凸块形成导电元件。 本发明有助于通过导电柱和导电凸块的金属球的对接的堆叠过程。

公开(公告)号：US10163662B2

公开(公告)日：2018-12-25

申请号：US15478508

申请日：2017-04-04

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Cheng-Chia Chiang ,  Don-Son Jiang ,  Lung-Yuan Wang ,  Shih-Hao Tung ,  Shu-Huei Huang

IPC: H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L21/48 ,  H01L23/538

Abstract: A semiconductor package is provided, which includes: a packaging substrate having opposite first and second surfaces and a plurality of first and second conductive pads formed on the first surface; a chip having opposite active and inactive surfaces and disposed on the first conductive pads via the active surface thereof; a plurality of conductive posts formed on the second conductive pads, respectively; and a first encapsulant formed on the first surface of the packaging substrate for encapsulating the chip and the conductive posts and having a plurality of openings for exposing upper surfaces of the conductive posts, thereby increasing the package density and protecting the chip and the interconnection structure from being adversely affected by intrusion of moisture.

公开(公告)号：US09343421B2

公开(公告)日：2016-05-17

申请号：US14309119

申请日：2014-06-19

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Lung-Yuan Wang ,  Cheng-Chia Chiang ,  Chu-Chi Hsu ,  Chia-Kai Shih ,  Shu-Huei Huang

IPC: H01L33/00 ,  H01L23/00 ,  H01L21/56 ,  H01L25/10 ,  H01L25/00 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538

CPC classification number: H01L25/50 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/19 ,  H01L24/73 ,  H01L24/96 ,  H01L25/105 ,  H01L2224/0231 ,  H01L2224/02331 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06548 ,  H01L2225/06562 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/29099 ,  H01L2224/13099 ,  H01L2924/00

Abstract: A method for fabricating a semiconductor package is provided, which includes the steps of: providing a first substrate having a plurality of first conductive posts on a surface thereof and providing a second substrate having a third surface having a chip disposed thereon and a fourth surface opposite to the third surface; disposing the first substrate on the third surface of the second substrate through the first conductive posts; forming an encapsulant between the first substrate and the second substrate, wherein the encapsulant has a first surface adjacent to the first substrate and a second surface opposite to the first surface; and removing the first substrate, thereby effectively preventing solder bridging from occurring.

Abstract translation: 提供一种制造半导体封装的方法，其包括以下步骤：提供在其表面上具有多个第一导电柱的第一衬底，并提供第二衬底，该第二衬底具有设置在其上的芯片的第三表面和与其相对的第四表面 到第三面; 通过第一导电柱将第一衬底设置在第二衬底的第三表面上; 在所述第一基板和所述第二基板之间形成密封剂，其中所述密封剂具有与所述第一基板相邻的第一表面和与所述第一表面相对的第二表面; 并移除第一基板，从而有效地防止焊料桥接发生。

公开(公告)号：US20150200169A1

公开(公告)日：2015-07-16

申请号：US14309119

申请日：2014-06-19

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Lung-Yuan Wang ,  Cheng-Chia Chiang ,  Chu-Chi Hsu ,  Chia-Kai Shih ,  Shu-Huei Huang

IPC: H01L23/00 ,  H01L23/31 ,  H01L21/56

CPC classification number: H01L25/50 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/19 ,  H01L24/73 ,  H01L24/96 ,  H01L25/105 ,  H01L2224/0231 ,  H01L2224/02331 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06548 ,  H01L2225/06562 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/29099 ,  H01L2224/13099 ,  H01L2924/00

Abstract: A method for fabricating a semiconductor package is provided, which includes the steps of: providing a first substrate having a plurality of first conductive posts on a surface thereof and providing a second substrate having a third surface having a chip disposed thereon and a fourth surface opposite to the third surface; disposing the first substrate on the third surface of the second substrate through the first conductive posts; forming an encapsulant between the first substrate and the second substrate, wherein the encapsulant has a first surface adjacent to the first substrate and a second surface opposite to the first surface; and removing the first substrate, thereby effectively preventing solder bridging from occurring.

Abstract translation: 提供一种制造半导体封装的方法，其包括以下步骤：提供在其表面上具有多个第一导电柱的第一衬底，并提供第二衬底，该第二衬底具有设置在其上的芯片的第三表面和与其相对的第四表面 到第三面; 通过第一导电柱将第一衬底设置在第二衬底的第三表面上; 在所述第一基板和所述第二基板之间形成密封剂，其中所述密封剂具有与所述第一基板相邻的第一表面和与所述第一表面相对的第二表面; 并移除第一基板，从而有效地防止焊料桥接发生。

公开(公告)号：US20150187722A1

公开(公告)日：2015-07-02

申请号：US14255326

申请日：2014-04-17

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Cheng-Chia Chiang ,  Don-Son Jiang ,  Lung-Yuan Wang ,  Shih-Hao Tung ,  Shu-Huei Huang

IPC: H01L23/00 ,  H01L23/31 ,  H01L21/56

CPC classification number: H01L21/563 ,  H01L21/4853 ,  H01L21/486 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05568 ,  H01L2224/05647 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81815 ,  H01L2224/92125 ,  H01L2924/14 ,  H01L2924/18161 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/014

Abstract: A semiconductor package is provided, which includes: a packaging substrate having opposite first and second surfaces and a plurality of first and second conductive pads formed on the first surface; a chip having opposite active and inactive surfaces and disposed on the first conductive pads via the active surface thereof; a plurality of conductive posts formed on the second conductive pads, respectively; and a first encapsulant formed on the first surface of the packaging substrate for encapsulating the chip and the conductive posts and having a plurality of openings for exposing upper surfaces of the conductive posts, thereby increasing the package density and protecting the chip and the interconnection structure from being adversely affected by intrusion of moisture.

Abstract translation: 提供一种半导体封装，其包括：具有相对的第一和第二表面的封装基板和形成在第一表面上的多个第一和第二导电焊盘; 具有相反的有源和无源表面的芯片，并经由其主动表面设置在第一导电焊盘上; 分别形成在所述第二导电焊盘上的多个导电柱; 以及形成在所述封装基板的所述第一表面上的第一密封剂，用于封装所述芯片和所述导电柱，并且具有用于暴露所述导电柱的上表面的多个开口，从而增加所述封装密度并保护所述芯片和所述互连结构 受到水分侵入的不利影响。