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公开(公告)号：US09818677B2
公开(公告)日：2017-11-14
申请号：US15202765
申请日：2016-07-06
发明人： Chun-Li Liu , Ali Salih , Balaji Padmanabhan , Mingjiao Liu
IPC分类号： H01L23/495 , H01L23/00 , H01L25/07 , H01L23/373 , H01L33/62 , H01L29/20
CPC分类号： H01L23/49575 , H01L23/3735 , H01L23/49524 , H01L23/49531 , H01L23/49555 , H01L23/49562 , H01L23/49568 , H01L24/73 , H01L25/072 , H01L29/2003 , H01L33/62 , H01L2224/40 , H01L2224/40245 , H01L2224/48091 , H01L2224/48137 , H01L2224/48245 , H01L2224/49111 , H01L2224/73221 , H01L2224/73265 , H01L2924/00014 , H01L2224/37099
摘要： In accordance with an embodiment, a semiconductor component is provided that includes a leadframe having a device receiving area, one or more leadframe leads and at least one insulated metal substrate bonded to a first portion of the device receiving area. A first semiconductor device is mounted to a first insulated metal substrate, the first semiconductor device configured from a III-N semiconductor material. A first electrical interconnect is coupled between the first current carrying terminal of the first semiconductor device and a second portion of the die receiving area. In accordance with another embodiment, method includes providing a first semiconductor chip comprising a III-N semiconductor substrate material and a second semiconductor chip comprising a silicon based semiconductor substrate. The first semiconductor chip is mounted on a first substrate and the second semiconductor chip on a second substrate. The first semiconductor chip is electrically coupled to the second semiconductor chip.
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公开(公告)号：US09748224B2
公开(公告)日：2017-08-29
申请号：US14853720
申请日：2015-09-14
发明人： Balaji Padmanabhan , Prasad Venkatraman , Zia Hossain , Chun-Li Liu , Jason McDonald , Ali Salih , Alexander Young
IPC分类号： H01L29/66 , H01L27/06 , H01L27/02 , H01L23/367 , H01L29/417 , H01L29/778 , H01L29/10 , H01L21/8258 , H01L21/74 , H01L29/872 , H01L23/48 , H01L29/861 , H01L29/20
CPC分类号： H01L27/0629 , H01L21/743 , H01L21/8258 , H01L23/3677 , H01L23/481 , H01L27/0255 , H01L27/0266 , H01L27/0688 , H01L29/1087 , H01L29/2003 , H01L29/41766 , H01L29/7783 , H01L29/861 , H01L29/872 , H01L2924/0002 , H01L2924/00
摘要： In one embodiment, a group III-V transistor structure includes a heterostructure disposed on a semiconductor substrate. A first current carrying electrode and a second current carrying electrode are disposed adjacent a major surface of the heterostructure and a control electrode is disposed between the first and second current carrying electrode. A clamping device is integrated with the group III-V transistor structure and is electrically connected to the first current carrying electrode a third electrode to provide a secondary current path during, for example, an electrical stress event.
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公开(公告)号：US09735095B2
公开(公告)日：2017-08-15
申请号：US15204604
申请日：2016-07-07
发明人： Balaji Padmanabhan , Prasad Venkatraman , Ali Salih , Chun-Li Liu
IPC分类号： H01L23/49 , H01L23/495 , H01L25/07 , H01L25/00
CPC分类号： H01L23/49575 , H01L23/49524 , H01L23/49531 , H01L23/49562 , H01L25/074 , H01L25/50 , H01L2224/0603 , H01L2224/16245 , H01L2224/40 , H01L2224/40245 , H01L2224/48091 , H01L2224/48247 , H01L2924/00014 , H01L2224/37099
摘要： In accordance with an embodiment, a semiconductor component includes a support having first and second device receiving structures. A semiconductor device configured from a III-N semiconductor material is coupled to the support, wherein the semiconductor device has opposing surfaces. A first bond pad extends from a first portion of the first surface, a second bond pad extends from a second portion of the first surface, and a third bond pad extends from a third portion of the first surface. The first bond pad is coupled to the first device receiving portion, the drain bond pad is coupled to the second device receiving portion, and the third bond pad is coupled to the third lead. In accordance with another embodiment, a method includes coupling a semiconductor chip comprising a III-N semiconductor substrate material to a support.
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公开(公告)号：US09660062B2
公开(公告)日：2017-05-23
申请号：US15133657
申请日：2016-04-20
IPC分类号： H01L29/66 , H01L29/747 , H01L29/74 , H01L27/088 , H01L23/495 , H01L29/205 , H01L29/40 , H01L29/423 , H01L29/778 , H01L25/11 , H03K17/687 , H01L23/00
CPC分类号： H01L29/747 , H01L21/8258 , H01L23/4952 , H01L23/49524 , H01L23/49541 , H01L23/49562 , H01L23/49575 , H01L24/40 , H01L25/115 , H01L25/18 , H01L27/0629 , H01L27/088 , H01L27/0883 , H01L29/205 , H01L29/404 , H01L29/4238 , H01L29/7416 , H01L29/742 , H01L29/7786 , H01L29/7787 , H01L2224/0603 , H01L2224/40245 , H01L2224/48247 , H01L2224/49113 , H01L2224/73221 , H01L2224/83801 , H01L2224/8385 , H01L2924/00014 , H03K17/6874 , H03K2017/6878 , H03K2217/0009 , H03K2217/0018 , H01L2224/37099
摘要： An electronic device can include a bidirectional HEMT. In an aspect, a packaged electronic device can include the bidirectional HEMT can be part of a die having a die substrate connection that is configured to be at a fixed voltage, electrically connected to drain/source or source/drain depending on current flow through the bidirectional HEMT, or electrically float. In another aspect, the electronic device can include Kelvin connections on both the drain/source and source/drain side of the circuit. In a further embodiment, a circuit can include the bidirectional HEMT, switch transistors, and diodes with breakdown voltages to limit voltage swings at the drain/source and source/drain of the switch transistors.
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公开(公告)号：US20170025336A1
公开(公告)日：2017-01-26
申请号：US15202826
申请日：2016-07-06
发明人： Balaji Padmanabhan , Prasad Venkatraman , Ali Salih , Mihir Mudholkar , Chun-Li Liu , Jason McDonald
IPC分类号： H01L23/495 , H01L23/00
CPC分类号： H01L23/49575 , H01L23/49503 , H01L23/4951 , H01L23/49524 , H01L23/49531 , H01L23/49534 , H01L23/49541 , H01L23/49548 , H01L23/49558 , H01L23/49562 , H01L24/40 , H01L24/41 , H01L24/45 , H01L2224/40105 , H01L2224/40139 , H01L2224/40245 , H01L2224/41109 , H01L2224/41112 , H01L2224/41174 , H01L2224/48245 , H01L2224/83801 , H01L2224/84801 , H01L2924/00014 , H01L2924/10253 , H01L2924/1033 , H01L2924/13064 , H01L2924/13091 , H01L2224/37099 , H01L2224/45099
摘要： In accordance with an embodiment, a semiconductor component includes a support having a first device receiving structure and a second device receiving structure and a contact extension that is common to the first and second device receiving structures. The first device receiving structure includes a device receiving area and the second device receiving structure includes a drain contact area. A III-N based semiconductor chip has a drain bond pad bonded to the drain contact area and a source bond pad bonded to the contact extension and a gate bond pad bonded to an interconnect. A portion of the silicon based semiconductor chip is bonded to the support device receiving area. In accordance with another embodiment, a method for manufacturing the semiconductor component includes coupling a III-N based semiconductor chip to a portion of the support a silicon based semiconductor chip to another portion of the support.
摘要翻译： 根据实施例，半导体部件包括具有第一器件接收结构和第二器件接收结构的支撑件以及第一和第二器件接收结构共同的接触延伸部。 第一器件接收结构包括器件接收区域，第二器件接收结构包括漏极接触区域。 基于III-N的半导体芯片具有焊接到漏极接触区域的漏极接合焊盘和接合到接触延伸部的源极接合焊盘和键合到互连的栅极焊盘焊盘。 硅基半导体芯片的一部分结合到支撑装置接收区域。 根据另一个实施例，制造半导体部件的方法包括将基于III-N的半导体芯片与载体的一部分将硅基半导体芯片耦合到支撑体的另一部分。
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公开(公告)号：US20160043218A1
公开(公告)日：2016-02-11
申请号：US14452191
申请日：2014-08-05
发明人： Peter Moens , Chun-Li Liu
IPC分类号： H01L29/78 , H01L29/06 , H01L21/02 , H01L29/66 , H01L21/285 , H01L29/417 , H01L21/768 , H01L29/20 , H01L21/762
CPC分类号： H01L21/76898 , H01L21/0217 , H01L21/02178 , H01L21/743 , H01L21/746 , H01L21/7605 , H01L21/76224 , H01L21/763 , H01L29/2003 , H01L29/407 , H01L29/4175 , H01L29/66318 , H01L29/7786
摘要： In accordance with an embodiment, a method for manufacturing a semiconductor component includes forming a first trench through a plurality of layers of compound semiconductor material. An insulating material is formed on first and second sidewalls of the first trench and first and second sidewalls of the second trench and a trench fill material is formed in the first and second trenches. In accordance with another embodiment, the semiconductor component includes a plurality of layers of compound semiconductor material over a body of semiconductor material and first and second filled trenches extending into the plurality of layers of compound semiconductor material. The first trench has first and second sidewalls and a floor and a first dielectric liner over the first and second sidewalls and the second trench has first and second sidewalls and a floor and second dielectric liner over the first and second sidewalls of the second trench.
摘要翻译： 根据实施例，半导体部件的制造方法包括通过多层化合物半导体材料形成第一沟槽。 绝缘材料形成在第一沟槽的第一和第二侧壁以及第二沟槽的第一和第二侧壁上，沟槽填充材料形成在第一和第二沟槽中。 根据另一实施例，半导体部件包括半导体材料体上的多层化合物半导体材料以及延伸到多层化合物半导体材料中的第一和第二填充沟槽。 第一沟槽具有第一和第二侧壁以及在第一和第二侧壁上方的底板和第一电介质衬垫，并且第二沟槽具有第一和第二侧壁以及位于第二沟槽的第一和第二侧壁上的底板和第二电介质衬垫。
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公开(公告)号：US10978581B2
公开(公告)日：2021-04-13
申请号：US16387874
申请日：2019-04-18
发明人： Woochul Jeon , Chun-Li Liu , Ali Salih
IPC分类号： H01L29/778 , H01L29/423 , H01L29/06 , H01L23/58 , H01L23/495 , H01L27/088 , H01L29/16 , H01L29/20 , H01L29/40 , H01L29/417 , H01L29/10
摘要： Implementations of semiconductor devices may include: a plurality of drain fingers and a plurality of source fingers interdigitated with one another; at least one gate; and at gate bus formed to completely surround the plurality of drain fingers and the plurality of source fingers; wherein the gate bus is mechanically and electrically coupled to the at least one gate.
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8.发明授权公开(公告)号：US10593666B2
公开(公告)日：2020-03-17
申请号：US16215870
申请日：2018-12-11
发明人： Balaji Padmanabhan , Prasad Venkatraman , Zia Hossain , Chun-Li Liu , Jason McDonald , Ali Salih , Alexander Young
IPC分类号： H01L29/20 , H01L27/06 , H01L21/8258 , H01L21/74 , H01L23/367 , H01L29/417 , H01L29/778 , H01L29/10 , H01L27/02 , H01L29/872 , H01L23/48 , H01L29/861
摘要： A cascode switch structure includes a group III-V transistor structure having a first current carrying electrode, a second current carrying electrode and a first control electrode. A semiconductor MOSFET device includes a third current carrying electrode electrically connected to the first current carrying electrode, a fourth current carrying electrode electrically connected to the first control electrode, and a second control electrode. A first diode includes a first cathode electrode electrically connected to the second current carrying electrode and a first anode electrode. A second diode includes a second anode electrode electrically connected to the first anode electrode and a second cathode electrode electrically connected to the fourth current carrying electrode. In one embodiment, the group III-V transistor structure, the first diode, and the second diode are integrated within a common substrate.
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公开(公告)号：US10418472B2
公开(公告)日：2019-09-17
申请号：US15581170
申请日：2017-04-28
发明人： Peter Moens , Jia Guo , Ali Salih , Chun-Li Liu
IPC分类号： H01L29/778 , H01L29/66 , H01L21/02 , H01L29/417 , H01L29/20 , H01L29/10 , H01L29/205 , H01L29/40
摘要： An electronic device can include a HEMT including at least two channel layers. In an embodiment, a lower semiconductor layer overlies a lower channel layer, wherein the lower semiconductor layer has an aluminum content that is at least 10% of a total metal content of the lower semiconductor layer. An upper semiconductor layer overlies the upper channel layer, wherein the upper semiconductor layer has an aluminum content that is greater as compared to the lower semiconductor layer. In another embodiment, an electronic device can include stepped source and drain electrodes, so that lower contact resistance can be achieved. In a further embodiment, an absolute value of a difference between pinch-off or threshold voltages between different channel layers is greater than 1 V and allows current to be turned on or turned off for a channel layer without affecting another channel layer.
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公开(公告)号：US09905500B2
公开(公告)日：2018-02-27
申请号：US15202826
申请日：2016-07-06
发明人： Balaji Padmanabhan , Prasad Venkatraman , Ali Salih , Mihir Mudholkar , Chun-Li Liu , Jason McDonald
IPC分类号： H01L23/00 , H01L23/495
CPC分类号： H01L23/49575 , H01L23/49503 , H01L23/4951 , H01L23/49524 , H01L23/49531 , H01L23/49534 , H01L23/49541 , H01L23/49548 , H01L23/49558 , H01L23/49562 , H01L24/40 , H01L24/41 , H01L24/45 , H01L2224/40105 , H01L2224/40139 , H01L2224/40245 , H01L2224/41109 , H01L2224/41112 , H01L2224/41174 , H01L2224/48245 , H01L2224/83801 , H01L2224/84801 , H01L2924/00014 , H01L2924/10253 , H01L2924/1033 , H01L2924/13064 , H01L2924/13091 , H01L2224/37099 , H01L2224/45099
摘要： In accordance with an embodiment, a semiconductor component includes a support having a first device receiving structure and a second device receiving structure and a contact extension that is common to the first and second device receiving structures. The first device receiving structure includes a device receiving area and the second device receiving structure includes a drain contact area. A III-N based semiconductor chip has a drain bond pad bonded to the drain contact area and a source bond pad bonded to the contact extension and a gate bond pad bonded to an interconnect. A portion of the silicon based semiconductor chip is bonded to the support device receiving area. In accordance with another embodiment, a method for manufacturing the semiconductor component includes coupling a III-N based semiconductor chip to a portion of the support a silicon based semiconductor chip to another portion of the support.
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