公开(公告)号：US20240079355A1

公开(公告)日：2024-03-07

申请号：US18499527

申请日：2023-11-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin-su LEE ,  Hong Sik CHAE ,  Youn Soo KIM ,  Tae Kyun KIM ,  Youn Joung CHO

IPC: H01L23/64 ,  H10B12/00

CPC classification number: H01L23/642 ,  H10B12/30

Abstract: Provided a semiconductor device comprises, a plurality of semiconductor patterns spaced in a first direction; a plurality of mold insulating layers between the plurality of semiconductor patterns, a plurality of silicide patterns contacting the plurality of semiconductor patterns; and a plurality of first metal conductive films between the plurality of mold insulating layers and connected to each of the silicide patterns, wherein each of the silicide patterns includes a first sidewall that faces the semiconductor pattern, and a second sidewall which faces the first metal conductive film, the first sidewall of the silicide pattern and the second sidewall of the silicide pattern extends in the first direction, and the first sidewall of the silicide pattern and the second sidewall of the silicide pattern are curved surfaces.

公开(公告)号：US20240213017A1

公开(公告)日：2024-06-27

申请号：US18228220

申请日：2023-07-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Younghun SUNG ,  Sunhye HWANG ,  Sangho RHA ,  Seungjae SIM ,  Younseok CHOI ,  Byungkeun HWANG ,  Youn Joung CHO

IPC: H01L21/02 ,  C23C16/34 ,  C23C16/40 ,  C23C16/50 ,  C23C16/56 ,  H01L21/311

CPC classification number: H01L21/02164 ,  C23C16/345 ,  C23C16/401 ,  C23C16/50 ,  C23C16/56 ,  H01L21/02211 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/31116 ,  H10B43/27

Abstract: A method of manufacturing an integrated circuit device, the method including forming a doped silicon oxide film on a substrate by supplying, onto the substrate, a silicon precursor, an oxidant, and at least two dopant sources including dopant elements that are different from each other such that the doped silicon oxide film includes at least two dopant elements; forming a vertical hole in the doped silicon oxide film by dry-etching the doped silicon oxide film; and forming a vertical structure in the vertical hole, wherein the silicon precursor includes a monosilane compound, a disilane compound, a siloxane compound, or a combination thereof, and the silicon precursor includes a Si—H functional group, and a C1-C10 oxy group or a C1-C10 organoamino group.

公开(公告)号：US20230142732A1

公开(公告)日：2023-05-11

申请号：US18053157

申请日：2022-11-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Eun Hyea KO ,  Hoon HAN ,  Byung Keun HWANG ,  Jeong Ho MUN ,  Hyun-Ji SONG ,  Youn Joung CHO

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/775 ,  H01L21/28 ,  H01L29/66

CPC classification number: H01L21/823842 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/775 ,  H01L21/28088 ,  H01L21/823807 ,  H01L29/66439

Abstract: The present disclosure provides a method for manufacturing a semiconductor device using selective vapor deposition and selective desorption. The method for manufacturing a semiconductor device includes providing a first layer having a first surface, and forming a second layer on the first layer such that a portion of the first surface is not covered by the second layer. The second layer has a second surface that meets the first surface. An inhibitor layer is formed on the first surface and the second surface, and the inhibitor layer on the second surface is selectively removed to expose the second surface. An interest layer is formed on the second surface. Physical properties of the first layer are different from physical properties of the second layer.

公开(公告)号：US20180211842A1

公开(公告)日：2018-07-26

申请号：US15414913

申请日：2017-01-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Won Woong CHUNG ,  Sun hye HWANG ,  Youn Joung CHO ,  Jung Sik CHOI ,  Xiaobing ZHOU ,  Brian David REKKEN ,  Byung Keun HWANG ,  Michael David TELGENHOFF

IPC: H01L21/28 ,  H01L21/02

CPC classification number: H01L21/28282 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02211 ,  H01L21/0228

Abstract: A method for fabricating a semiconductor device includes forming a structure with a height difference on a substrate and forming a dielectric layer structure on the structure using an atomic layer deposition (ALD) method. Forming the dielectric layer structure includes forming a first dielectric layer including silicon nitride on the structure with the height difference. Forming the first dielectric layer includes feeding a first gas including pentachlorodisilane (PCDS) or diisopropylamine pentachlorodisilane (DPDC) as a silicon precursor, and a second gas including nitrogen components into a chamber including the substrate such that the first dielectric layer is formed in situ on the structure having the height difference.

公开(公告)号：US20230282475A1

公开(公告)日：2023-09-07

申请号：US18098856

申请日：2023-01-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Eun Hyea KO ,  Hoon HAN ,  Byung Keun HWANG ,  Jae Woon KIM ,  Jeong Ho MUN ,  Younghun SUNG ,  Hyun-Ji SONG ,  Youn Joung CHO

IPC: H01L21/02 ,  G03F7/038 ,  H01L21/311 ,  H01L21/56 ,  G03F7/16 ,  G03F7/09

CPC classification number: H01L21/02118 ,  G03F7/0387 ,  G03F7/094 ,  G03F7/168 ,  H01L21/02205 ,  H01L21/02255 ,  H01L21/0228 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/56

Abstract: A semiconductor device manufacturing method includes providing a first layer having a first surface, providing a second layer including a trench that exposes the first surface, onto the first layer, forming a first polymer layer that fills the trench, and performing a heat treatment process on the first polymer layer to form a second polymer layer. A second surface of the second layer is exposed by the trench, the first polymer layer includes a first portion being in contact with the first surface, and a second portion being in contact with the second surface, when the heat treatment process is performed, the first portion of the first polymer layer is decomposed, when the heat treatment process is performed, the second portion of the first polymer layer is cross-linked to form the second polymer layer, and physical properties of the first layer are different from physical properties of the second layer.

公开(公告)号：US20220093532A1

公开(公告)日：2022-03-24

申请号：US17470370

申请日：2021-09-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin-su LEE ,  Hong Sik CHAE ,  Youn Soo KIM ,  Tae Kyun KIM ,  Youn Joung CHO

IPC: H01L23/64 ,  H01L27/108

Abstract: Provided a semiconductor device comprises, a plurality of semiconductor patterns spaced in a first direction; a plurality of mold insulating layers between the plurality of semiconductor patterns, a plurality of silicide patterns contacting the plurality of semiconductor patterns; and a plurality of first metal conductive films between the plurality of mold insulating layers and connected to each of the silicide patterns, wherein each of the silicide patterns includes a first sidewall that faces the semiconductor pattern, and a second sidewall which faces the first metal conductive film, the first sidewall of the silicide pattern and the second sidewall of the silicide pattern extends in the first direction, and the first sidewall of the silicide pattern and the second sidewall of the silicide pattern are curved surfaces.

公开(公告)号：US20170170023A1

公开(公告)日：2017-06-15

申请号：US15291268

申请日：2016-10-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Won Woong CHUNG ,  Youn Joung CHO ,  Jung Sik CHOI

IPC: H01L21/285 ,  H01L21/768 ,  H01L21/8238

CPC classification number: H01L21/28518 ,  H01L21/2855 ,  H01L21/76843 ,  H01L21/76895 ,  H01L21/823814 ,  H01L21/823871 ,  H01L21/823878 ,  H01L23/485 ,  H01L29/66515 ,  H01L29/66545 ,  H01L29/78

Abstract: There is provides a method of fabricating a semiconductor device to decrease contact resistance of source/drain regions and gate electrodes and thereby improve operation performance. The method includes providing an exposed silicon region, forming a rare earth metal silicide film on the exposed silicon region, the rare earth metal silicide film contacting the silicon region, and forming a contact on the rare earth metal silicide film, the contact being electrically connected to the exposed silicon region, wherein the rare earth metal silicide film is formed by simultaneously supplying a rare earth metal and silicon to the exposed silicon region using physical vapor deposition.