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    Integrated circuit device
    1.
    发明授权
    Integrated circuit device 有权

    公开(公告)号：US12068418B2

    公开(公告)日：2024-08-20

    申请号：US17580717

    申请日：2022-01-21

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Kyongsik Yeom ,  Youngcheon Jeong ,  Yongkyu Lee

    IPC: H01L29/423 ,  H01L29/66 ,  H01L29/788 ,  H10B41/35 ,  H10B41/41

    CPC classification number: H01L29/788 ,  H01L29/42328 ,  H01L29/42336 ,  H01L29/6656 ,  H01L29/66825 ,  H10B41/35 ,  H10B41/41

    Abstract: An integrated circuit includes; a source region arranged in an upper portion of a substrate, a pair of split gate structures respectively on opposing sides of the source region, wherein each of the pair of split gate structures includes a floating gate electrode layer and a control gate electrode layer disposed on the floating gate electrode layer, an erase gate structure between the pair of split gate structures on the source region and including an erase gate electrode layer, a pair of selection gate structures respectively on outer sidewalls of the pair of split gate structures, and a pair of gate spacers, wherein each of the gate spacers is disposed between one of the pair of split gate structures and one of the pair of selection gate structures, includes a first gate spacer and a second gate spacer disposed on the first gate spacer, is further disposed on an outer side wall of the one of the pair of split gate structures, and a lowermost end of the second gate spacer is at a lower level than an upper surface of the floating gate electrode layer.

    RESISTIVE MEMORY DEVICE
    2.
    发明申请
    RESISTIVE MEMORY DEVICE 有权
    电阻式存储器件

    公开(公告)号：US20140204652A1

    公开(公告)日：2014-07-24

    申请号：US14069499

    申请日：2013-11-01

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Yongkyu Lee ,  Sungyeon Lee ,  Yeongtaek Lee

    IPC: G11C13/00

    CPC classification number: G11C13/004 ,  G11C7/1075 ,  G11C8/16 ,  G11C11/005 ,  G11C11/5607 ,  G11C11/5614 ,  G11C11/5642 ,  G11C11/5657 ,  G11C11/5678 ,  G11C29/50008 ,  G11C29/52 ,  G11C2013/0054 ,  G11C2029/0409 ,  G11C2029/0411 ,  G11C2213/72

    Abstract: A resistive memory device includes memory cell array blocks, a reference cell array block, two first and second sink transistors, and a word line. Each of the memory cell array blocks includes a row line, and the reference cell array block includes a reference row line. One of the first sink transistors is disposed between one end of the row line and a ground and the other of the first sink transistors is disposed between an opposite end of the row line and the ground. One of the second sink transistors is disposed between one end of the reference row line and the ground and the other of the second sink transistors is disposed between an opposite end of the reference row line and the ground. The word line is coupled to gates of the first and second sink transistors.

    Abstract translation: 电阻式存储器件包括存储单元阵列块，参考单元阵列块，两个第一和第二宿晶体管以及字线。 每个存储单元阵列块包括行线，并且参考单元阵列块包括参考行线。 第一个晶体管中的一个设置在行线的一端和地之间，而另一个第一宿晶体管设置在行线的相对端和地之间。 第二宿晶体管中的一个设置在参考行线的一端和地之间，另一个第二宿晶体管设置在参考行线的相对端和地之间。 字线耦合到第一和第二宿晶体管的栅极。

    Memory device
    3.
    发明授权
    Memory device 有权

    公开(公告)号：US12302575B2

    公开(公告)日：2025-05-13

    申请号：US17725993

    申请日：2022-04-21

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Kyongsik Yeom ,  Changmin Jeon ,  Yongkyu Lee

    IPC: H01L23/535 ,  H01L27/11582 ,  H10B43/35

    Abstract: A memory device includes a first bit line configured to supply a first bit line bias voltage, a memory cell transistor having a first operating voltage, a selection transistor having a second operating voltage and configured to control the supply of the first bit line bias voltage to a source of the memory cell transistor, and a second bit line connected to a drain of the memory cell transistor. A level of the first operating voltage is about equal to a level of the second operating voltage.

    INTEGRATED CIRCUIT DEVICE
    8.
    发明公开
    INTEGRATED CIRCUIT DEVICE 审中-公开

    公开(公告)号：US20240363764A1

    公开(公告)日：2024-10-31

    申请号：US18768737

    申请日：2024-07-10

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Kyongsik Yeom ,  Youngcheon Jeong ,  Yongkyu Lee

    IPC: H01L29/788 ,  H01L29/423 ,  H01L29/66 ,  H10B41/35 ,  H10B41/41

    CPC classification number: H01L29/788 ,  H01L29/42328 ,  H01L29/42336 ,  H01L29/6656 ,  H01L29/66825 ,  H10B41/35 ,  H10B41/41

    Abstract: An integrated circuit includes: a source region, split gate structures on opposing sides of the source region, the split gate structures including a floating gate electrode layer and a control gate electrode layer, an erase gate structure between the split gate structures on the source region and including an erase gate electrode layer, a pair of selection gate structures on outer sidewalls of the split gate structures, and a pair of gate spacers. Each gate spacer is disposed between one of the split gate structures and one of the selection gate structures, includes a first gate spacer and a second gate spacer disposed on the first gate spacer, and is further disposed on an outer side wall of the one of the split gate structures. A lowermost end of the second gate spacer is at a lower level than an upper surface of the floating gate electrode layer.

    Magnetic memory devices
    9.
    发明授权
    Magnetic memory devices 有权

    公开(公告)号：US10515678B2

    公开(公告)日：2019-12-24

    申请号：US16285295

    申请日：2019-02-26

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Boyoung Seo ,  Seongui Seo ,  Gwanhyeob Koh ,  Yongkyu Lee

    IPC: G11C11/16 ,  H01L27/22

    Abstract: A magnetic memory device includes a substrate, a landing pad on the substrate, first and second magnetic tunnel junction patterns disposed on the interlayer insulating layer and spaced apart from the landing pad when viewed from a plan view, and an interconnection structure electrically connecting a top surface of the second magnetic tunnel junction pattern to the landing pad. A distance between the landing pad and the first magnetic tunnel junction pattern is greater than a distance between the first and second magnetic tunnel junction patterns, and a distance between the landing pad and the second magnetic tunnel junction pattern is greater than the distance between the first and second magnetic tunnel junction patterns, when viewed from a plan view.

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