公开(公告)号：US11728311B2

公开(公告)日：2023-08-15

申请号：US17187985

申请日：2021-03-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Shaofeng Ding ,  Jeong Hoon Ahn ,  Yun Ki Choi

IPC: H01L23/522 ,  H01L25/065 ,  H01L23/64 ,  H01L23/528 ,  H01L23/498 ,  H01L23/48

CPC classification number: H01L25/0652 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/5223 ,  H01L23/5286 ,  H01L23/642

Abstract: A semiconductor device includes an interposer substrate and at least one die mounted on the interposer substrate. The interposer substrate includes a semiconductor substrate having a first surface and a second surface opposite to the first surface, an interlayer insulating layer on the first surface of the semiconductor substrate, a capacitor in a hole penetrating the interlayer insulating layer, an interconnection layer on the interlayer insulating layer, and a through-via extending from the interconnection layer toward the second surface of the semiconductor substrate in a vertical direction that is perpendicular to the first surface of the semiconductor substrate. The capacitor includes a sequential stack of a first electrode, a first dielectric layer, a second electrode, a second dielectric layer and a third electrode. A bottom of the hole is distal from the second surface of the semiconductor substrate in relation to the first surface of the semiconductor substrate.

公开(公告)号：US12279408B2

公开(公告)日：2025-04-15

申请号：US18405736

申请日：2024-01-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Shaofeng Ding ,  Jeong Hoon Ahn ,  Yun Ki Choi

IPC: H10B10/00 ,  H01L21/02 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786 ,  H10B12/00

Abstract: A semiconductor device includes a substrate including a logic cell region and a connection region, a dummy transistor on the connection region, an intermediate connection layer on the dummy transistor, the intermediate connection layer including a connection pattern electrically connected to the dummy transistor, a first metal layer on the intermediate connection layer, an etch stop layer between the intermediate connection layer and the first metal layer, the etch stop layer covering a top surface of the connection pattern, and a penetration contact extended from the first metal layer toward a bottom surface of the substrate penetrating the connection region.

公开(公告)号：US20200343178A1

公开(公告)日：2020-10-29

申请号：US16596074

申请日：2019-10-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Shaofeng Ding ,  Jeonghoon Ahn

IPC: H01L23/522 ,  H01L23/532 ,  H01L23/00 ,  H01L49/02 ,  H01L21/768

Abstract: A semiconductor device includes a first electrode disposed on a substrate. A capacitor dielectric layer is on the first electrode. A second electrode is on the capacitor dielectric layer. A first insulating layer is on the first and second electrodes and the capacitor dielectric layer. A first interconnection structure is on the first insulating layer and connected to the first electrode. A second interconnection structure is on the first insulating layer and connected to the second electrode. A second insulating layer is on the first and second interconnection structures. A plurality of connection structures are configured to pass through the second insulating layer and be connected to the first and second interconnection structures. Each of the first and second interconnection structures has an aluminum layer.

公开(公告)号：US12107034B2

公开(公告)日：2024-10-01

申请号：US17517291

申请日：2021-11-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Shaofeng Ding ,  Sungwook Moon ,  Jeonghoon Ahn ,  Yunki Choi

IPC: H01L21/00 ,  H01L23/48 ,  H01L23/522 ,  H01L25/065

CPC classification number: H01L23/481 ,  H01L23/5226 ,  H01L25/0657 ,  H01L2225/06541

Abstract: A semiconductor chip may include; a device layer including transistors on a substrate, a wiring layer on the device layer, a first through via passing through the device layer and the substrate, and a second through via passing through the wiring layer, the device layer and the substrate, wherein a first height of the first through via is less than a second height of the second through via.

公开(公告)号：US11955509B2

公开(公告)日：2024-04-09

申请号：US17559176

申请日：2021-12-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jihyung Kim ,  Jeonghoon Ahn ,  Jaehee Oh ,  Shaofeng Ding ,  Wonji Park ,  Jegwan Hwang

IPC: H01L23/522 ,  H01L23/52 ,  H01L49/02

CPC classification number: H01L28/65 ,  H01L23/5223 ,  H01L28/87

Abstract: A metal-insulator-metal capacitor includes a first electrode disposed in a first region of an upper surface of a substrate, a second electrode covering the first electrode and extending to a second region surrounding an outer periphery of the first region, a third electrode covering the second electrode and extending to a third region surrounding an outer periphery of the second region, a first dielectric layer disposed between the first electrode and the second electrode to cover an upper surface and a side surface of the first electrode and extending to the second region, and a second dielectric layer disposed between the second electrode and the third electrode to cover an upper surface and a side surface of the second electrode and extending to the third region and in contact with the first dielectric layer.

公开(公告)号：US11871553B2

公开(公告)日：2024-01-09

申请号：US17474436

申请日：2021-09-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Shaofeng Ding ,  Jeong Hoon Ahn ,  Yun Ki Choi

IPC: H01L27/11 ,  H01L27/108 ,  H01L27/092 ,  H01L29/78 ,  H01L29/08 ,  H01L29/417 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/66 ,  H10B10/00 ,  H10B12/00

CPC classification number: H10B10/18 ,  H01L21/0259 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823871 ,  H01L27/092 ,  H01L29/0665 ,  H01L29/0847 ,  H01L29/41733 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/78618 ,  H01L29/78696 ,  H10B12/50

Abstract: A semiconductor device includes a substrate including a logic cell region and a connection region, a dummy transistor on the connection region, an intermediate connection layer on the dummy transistor, the intermediate connection layer including a connection pattern electrically connected to the dummy transistor, a first metal layer on the intermediate connection layer, an etch stop layer between the intermediate connection layer and the first metal layer, the etch stop layer covering a top surface of the connection pattern, and a penetration contact extended from the first metal layer toward a bottom surface of the substrate penetrating the connection region.

公开(公告)号：US11791267B2

公开(公告)日：2023-10-17

申请号：US17340584

申请日：2021-06-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinho Park ,  Shaofeng Ding ,  Yongseung Bang ,  Jeong Hoon Ahn

IPC: H01L23/522 ,  H01L23/535 ,  H10B12/00

CPC classification number: H01L23/535 ,  H10B12/00

Abstract: A semiconductor device includes a substrate, a first electrode including a first hole, a first dielectric layer on an upper surface of the first electrode and on an inner surface of the first hole, a second electrode on the first dielectric layer, a second dielectric layer on the second electrode, a third electrode on the second dielectric layer and including a second hole, and a first contact plug extending through the second electrode and the second dielectric layer and extending through the first hole and the second hole. A sidewall of the first contact plug is isolated from direct contact with the sidewall of the first hole and a sidewall of the second hole, and has a step portion located adjacent to an upper surface of the second electrode.

公开(公告)号：US11538747B2

公开(公告)日：2022-12-27

申请号：US16881452

申请日：2020-05-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Shaofeng Ding ,  Jae June Jang ,  Jeong Hoon Ahn ,  Yun Ki Choi

IPC: H01L29/76 ,  H01L29/00 ,  H01L23/522 ,  H01L49/02 ,  H01L23/48 ,  H01L23/498

Abstract: Provided is an interposer structure. The interposer structure comprises an interposer substrate, an interlayer insulating film which covers a top surface of the interposer substrate, a capacitor structure in the interlayer insulating film and a wiring structure including a first wiring pattern and a second wiring pattern spaced apart from the first wiring pattern, on the interlayer insulating film, wherein the capacitor structure includes an upper electrode connected to the first wiring pattern, a lower electrode connected to the second wiring pattern, and a capacitor dielectric film between the upper electrode and the lower electrode.

公开(公告)号：US11437374B2

公开(公告)日：2022-09-06

申请号：US17034296

申请日：2020-09-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Shaofeng Ding ,  Minguk Kang ,  Jihyung Kim ,  Jeong Hoon Ahn ,  Haeri Yoo ,  Yun Ki Choi

IPC: H01L27/092 ,  H01L25/065 ,  H01L27/02 ,  H01L29/417 ,  H01L21/768 ,  H01L27/088 ,  H01L29/165 ,  H01L29/08 ,  B82Y10/00 ,  H01L29/66 ,  H01L29/423 ,  H01L29/786 ,  H01L29/06 ,  H01L29/775 ,  H01L21/8238 ,  H01L23/522 ,  H01L25/18 ,  H01L21/8234 ,  H01L27/108 ,  H01L27/11 ,  H01L23/485 ,  H01L23/48 ,  H01L29/78

Abstract: A semiconductor device includes a substrate including a logic cell region and a connection region, a dummy transistor on the connection region, an intermediate connection layer on the dummy transistor, a first metal layer on the intermediate connection layer, an etch stop layer between the intermediate connection layer and the first metal layer, a through contact below the first metal layer penetrating the connection region, an upper portion of the through contact protruding above the etch stop layer, and a protection insulating pattern on the etch stop layer covering the upper portion of the through contact. The protection insulating pattern covers an upper side surface of the through contact and a top surface of the through contact.

公开(公告)号：US20200075712A1

公开(公告)日：2020-03-05

申请号：US16379016

申请日：2019-04-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Shaofeng Ding ,  Jeong Hoon Ahn

IPC: H01L49/02 ,  H01L23/522 ,  H01L23/48 ,  H01L29/49 ,  H01L21/768

Abstract: Semiconductor devices including a capacitor in which electrostatic capacity is improved by a simplified process and/or methods for fabricating the same are provided. The semiconductor device including an insulating structure defining a first trench on a substrate, a first conductive layer in the insulating structure, a first portion of an upper surface of the first conductive layer exposed by the first trench, a capacitor structure including a first electrode pattern on the first conductive layer, a dielectric pattern on the first electrode pattern, and a second electrode pattern on the dielectric pattern, the first electrode pattern extending along sidewalls and a bottom surface of the first trench and an upper surface of the insulating structure, and a first wiring pattern on the capacitor structure may be provided.