公开(公告)号：US09911688B2

公开(公告)日：2018-03-06

申请号：US15201694

申请日：2016-07-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyo-Seon Choi ,  Seungmo Kang ,  Sang-ki Kim ,  Yooncheol Bang

IPC: H01L21/00 ,  H01L23/498 ,  H01L23/544 ,  H01L23/00 ,  H01L23/50 ,  H01L23/31

CPC classification number: H01L23/49838 ,  H01L23/291 ,  H01L23/3128 ,  H01L23/3192 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/50 ,  H01L23/544 ,  H01L24/03 ,  H01L24/05 ,  H01L24/09 ,  H01L2224/02313 ,  H01L2224/02317 ,  H01L2224/0235 ,  H01L2224/02375 ,  H01L2224/02379 ,  H01L2224/0345 ,  H01L2224/03622 ,  H01L2224/0392 ,  H01L2224/04042 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/06131 ,  H01L2224/06135 ,  H01L2224/06151 ,  H01L2224/06155 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/06565 ,  H01L2924/1436 ,  H01L2924/15311 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A semiconductor device includes a semiconductor chip substrate with a chip region and a scribe lane region, center and boundary pads respectively provided on the chip and scribe lane regions, a lower insulating structure provided on the chip region and the scribe lane region, a first conductive pattern including a contact portion, a conductive line portion, and a bonding pad portion, and an upper insulating structure defining first and second openings formed on the bonding pad portion and the boundary pad. The lower insulating structure includes a plurality of lower insulating layers, which are sequentially stacked on the substrate, and each of which is a silicon-containing inorganic layer.

公开(公告)号：US08749071B2

公开(公告)日：2014-06-10

申请号：US13908220

申请日：2013-06-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong-Sik Park ,  Sungjin Kim ,  Seungmo Kang

IPC: H01L29/45 ,  H01L23/48

CPC classification number: H01L23/53257 ,  H01L21/7682 ,  H01L21/76858 ,  H01L21/76885 ,  H01L23/5222 ,  H01L23/5283 ,  H01L23/53223 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device may include a first interlayer dielectric layer including a plurality of contacts, a plurality of interconnection patterns disposed on the first interlayer dielectric layer and connected to the contacts, respectively, and a second interlayer dielectric layer disposed on the first interlayer dielectric layer and covering the interconnection patterns. Each of the interconnection patterns may include a first metal pattern, a second metal pattern disposed on the first metal pattern, a first barrier pattern between the contact and the first metal pattern, and a second barrier pattern between the first metal pattern and the second metal pattern. The second metal pattern may expose a portion of a top surface of the second barrier pattern, and the second interlayer dielectric layer may include an air gap between the interconnection patterns adjacent to each other.

Abstract translation: 半导体器件可以包括：第一层间介质层，包括多个触点;多个互连图案，分别设置在第一层间电介质层上并分别连接到触点;以及第二层间介质层，设置在第一层间介质层上， 涵盖互连模式。 每个互连图案可以包括第一金属图案，设置在第一金属图案上的第二金属图案，接触件和第一金属图案之间的第一阻挡图案，以及第一金属图案和第二金属图案之间的第二阻挡图案 模式。 第二金属图案可以暴露第二阻挡图案的顶表面的一部分，并且第二层间电介质层可以包括彼此相邻的互连图案之间的气隙。

公开(公告)号：US09735121B2

公开(公告)日：2017-08-15

申请号：US15222114

申请日：2016-07-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ahyun Jo ,  Seungmo Kang ,  Yooncheol Bang ,  Seokwoo Hong

IPC: H01L23/58 ,  H01L29/10 ,  H01L23/00 ,  H01L21/66 ,  H01L23/31 ,  H01L25/065

CPC classification number: H01L24/09 ,  H01L22/14 ,  H01L22/32 ,  H01L23/291 ,  H01L23/3128 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/33 ,  H01L25/0657 ,  H01L2224/02313 ,  H01L2224/0235 ,  H01L2224/02375 ,  H01L2224/02379 ,  H01L2224/0345 ,  H01L2224/03622 ,  H01L2224/0392 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/04042 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/06135 ,  H01L2224/06151 ,  H01L2224/06155 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/06565 ,  H01L2924/1436 ,  H01L2924/15311 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A semiconductor chip and/or a semiconductor package including the same are disclosed. The semiconductor chip may include an integrated circuit on a substrate, a center pad electrically connected to the integrated circuit, a lower insulating structure on the center pad and having a contact hole exposing the center pad, the lower insulating structure including a plurality of lower insulating layers sequentially stacked on the substrate, a conductive pattern including a contact portion, a pad portion, a conductive line portion, the contact portion filling the contact hole, the pad portion including a test region and a bonding region, a conductive line portion on the lower insulating structure and connecting the contact portion to the pad portion, and an upper insulating structure on the conductive pattern and having a first opening exposing the pad portion, and the upper insulating structure including an upper insulating layer and a polymer layer.

公开(公告)号：US20250142814A1

公开(公告)日：2025-05-01

申请号：US18667445

申请日：2024-05-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yonghyeok Son ,  Jeongil Seo ,  Donghun Lee ,  Seungmo Kang ,  Seung Joo Lee ,  Yujin Cho ,  Seongjun Choi

IPC: H10B12/00

Abstract: A semiconductor device includes an interconnection line, an insulating layer on the interconnection line and having an opening exposing a top surface of the interconnection line, and a redistribution pattern extending into the opening and electrically connected to the interconnection line at a bottom surface of the opening. The interconnection line is configured to provide a current path in a first direction in a region adjacent to the redistribution pattern. The opening comprises a first side surface facing the first direction. A corner region of the opening protrudes away from or is recessed towards the opening at an end portion of the first side surface of the opening when viewed in plan view.

公开(公告)号：US10950508B2

公开(公告)日：2021-03-16

申请号：US16711771

申请日：2019-12-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seongrak Jeong ,  Seungmo Kang

IPC: H01L21/66 ,  H01L21/265 ,  G06N3/08 ,  C23C14/48 ,  C23C14/54 ,  G06N3/04 ,  H01J37/317

Abstract: An ion depth profile control method includes performing reinforcement learning, whereby a similarity between an ion depth profile and a box profile is output as a reward when the similarity is equal to or greater than a set criterion, the ion depth profile being an ion concentration according to a wafer depth in an ion implantation process, and the box profile being a target profile, obtaining at least one process condition of the ion implantation process as a result of the reinforcement learning, and generating a process recipe regarding the at least one process condition.

公开(公告)号：US20140015137A1

公开(公告)日：2014-01-16

申请号：US13908220

申请日：2013-06-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong-Sik Park ,  Sungjin Kim ,  Seungmo Kang

IPC: H01L23/532

CPC classification number: H01L23/53257 ,  H01L21/7682 ,  H01L21/76858 ,  H01L21/76885 ,  H01L23/5222 ,  H01L23/5283 ,  H01L23/53223 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device may include a first interlayer dielectric layer including a plurality of contacts, a plurality of interconnection patterns disposed on the first interlayer dielectric layer and connected to the contacts, respectively, and a second interlayer dielectric layer disposed on the first interlayer dielectric layer and covering the interconnection patterns. Each of the interconnection patterns may include a first metal pattern, a second metal pattern disposed on the first metal pattern, a first barrier pattern between the contact and the first metal pattern, and a second barrier pattern between the first metal pattern and the second metal pattern. The second metal pattern may expose a portion of a top surface of the second barrier pattern, and the second interlayer dielectric layer may include an air gap between the interconnection patterns adjacent to each other.

Abstract translation: 半导体器件可以包括：第一层间介质层，包括多个触点;多个互连图案，分别设置在第一层间电介质层上并分别连接到触点;以及第二层间介质层，设置在第一层间介质层上， 涵盖互连模式。 每个互连图案可以包括第一金属图案，设置在第一金属图案上的第二金属图案，接触件和第一金属图案之间的第一阻挡图案，以及第一金属图案和第二金属图案之间的第二阻挡图案 模式。 第二金属图案可以暴露第二阻挡图案的顶表面的一部分，并且第二层间电介质层可以包括彼此相邻的互连图案之间的气隙。