公开(公告)号：US09911688B2

公开(公告)日：2018-03-06

申请号：US15201694

申请日：2016-07-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyo-Seon Choi ,  Seungmo Kang ,  Sang-ki Kim ,  Yooncheol Bang

IPC: H01L21/00 ,  H01L23/498 ,  H01L23/544 ,  H01L23/00 ,  H01L23/50 ,  H01L23/31

CPC classification number: H01L23/49838 ,  H01L23/291 ,  H01L23/3128 ,  H01L23/3192 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/50 ,  H01L23/544 ,  H01L24/03 ,  H01L24/05 ,  H01L24/09 ,  H01L2224/02313 ,  H01L2224/02317 ,  H01L2224/0235 ,  H01L2224/02375 ,  H01L2224/02379 ,  H01L2224/0345 ,  H01L2224/03622 ,  H01L2224/0392 ,  H01L2224/04042 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/06131 ,  H01L2224/06135 ,  H01L2224/06151 ,  H01L2224/06155 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/06565 ,  H01L2924/1436 ,  H01L2924/15311 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A semiconductor device includes a semiconductor chip substrate with a chip region and a scribe lane region, center and boundary pads respectively provided on the chip and scribe lane regions, a lower insulating structure provided on the chip region and the scribe lane region, a first conductive pattern including a contact portion, a conductive line portion, and a bonding pad portion, and an upper insulating structure defining first and second openings formed on the bonding pad portion and the boundary pad. The lower insulating structure includes a plurality of lower insulating layers, which are sequentially stacked on the substrate, and each of which is a silicon-containing inorganic layer.

公开(公告)号：US09735121B2

公开(公告)日：2017-08-15

申请号：US15222114

申请日：2016-07-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ahyun Jo ,  Seungmo Kang ,  Yooncheol Bang ,  Seokwoo Hong

IPC: H01L23/58 ,  H01L29/10 ,  H01L23/00 ,  H01L21/66 ,  H01L23/31 ,  H01L25/065

CPC classification number: H01L24/09 ,  H01L22/14 ,  H01L22/32 ,  H01L23/291 ,  H01L23/3128 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/33 ,  H01L25/0657 ,  H01L2224/02313 ,  H01L2224/0235 ,  H01L2224/02375 ,  H01L2224/02379 ,  H01L2224/0345 ,  H01L2224/03622 ,  H01L2224/0392 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/04042 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/06135 ,  H01L2224/06151 ,  H01L2224/06155 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/06565 ,  H01L2924/1436 ,  H01L2924/15311 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A semiconductor chip and/or a semiconductor package including the same are disclosed. The semiconductor chip may include an integrated circuit on a substrate, a center pad electrically connected to the integrated circuit, a lower insulating structure on the center pad and having a contact hole exposing the center pad, the lower insulating structure including a plurality of lower insulating layers sequentially stacked on the substrate, a conductive pattern including a contact portion, a pad portion, a conductive line portion, the contact portion filling the contact hole, the pad portion including a test region and a bonding region, a conductive line portion on the lower insulating structure and connecting the contact portion to the pad portion, and an upper insulating structure on the conductive pattern and having a first opening exposing the pad portion, and the upper insulating structure including an upper insulating layer and a polymer layer.