公开(公告)号：US10090266B2

公开(公告)日：2018-10-02

申请号：US15205414

申请日：2016-07-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ae-Hee Choi ,  Sang-ki Kim ,  Ahyun Jo ,  Kyo-Seon Choi

IPC: H01L23/00 ,  H01L21/00 ,  H01L23/58 ,  H01L29/10 ,  H01L21/66 ,  H01L23/31 ,  H01L25/065 ,  H01L23/498 ,  H01L23/544 ,  H01L23/50 ,  H01L25/00

Abstract: A semiconductor device includes a semiconductor chip having a semiconductor substrate with chip and boundary regions, and an integrated circuit on the chip region. A center pad is provided on the chip region and on the integrated circuit, and a boundary pad is provided on the boundary region. The semiconductor device further includes a first lower insulating structure having a contact hole exposing the center pad, a second lower insulating structure, at the same vertical level as the first lower insulating structure, and having a first opening exposing the boundary pad to an outside of the first lower insulating structure, a conductive pattern including a contact portion, a conductive line portion, and a bonding pad portion, and an upper insulating structure formed on the first lower insulating structure and the conductive pattern and having a second opening exposing the bonding pad portion to the outside of the semiconductor chip. The first lower insulating structure has a top surface positioned at a higher vertical level than that of the second lower insulating structure.

公开(公告)号：US09911688B2

公开(公告)日：2018-03-06

申请号：US15201694

申请日：2016-07-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyo-Seon Choi ,  Seungmo Kang ,  Sang-ki Kim ,  Yooncheol Bang

IPC: H01L21/00 ,  H01L23/498 ,  H01L23/544 ,  H01L23/00 ,  H01L23/50 ,  H01L23/31

CPC classification number: H01L23/49838 ,  H01L23/291 ,  H01L23/3128 ,  H01L23/3192 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/50 ,  H01L23/544 ,  H01L24/03 ,  H01L24/05 ,  H01L24/09 ,  H01L2224/02313 ,  H01L2224/02317 ,  H01L2224/0235 ,  H01L2224/02375 ,  H01L2224/02379 ,  H01L2224/0345 ,  H01L2224/03622 ,  H01L2224/0392 ,  H01L2224/04042 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/06131 ,  H01L2224/06135 ,  H01L2224/06151 ,  H01L2224/06155 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/06565 ,  H01L2924/1436 ,  H01L2924/15311 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A semiconductor device includes a semiconductor chip substrate with a chip region and a scribe lane region, center and boundary pads respectively provided on the chip and scribe lane regions, a lower insulating structure provided on the chip region and the scribe lane region, a first conductive pattern including a contact portion, a conductive line portion, and a bonding pad portion, and an upper insulating structure defining first and second openings formed on the bonding pad portion and the boundary pad. The lower insulating structure includes a plurality of lower insulating layers, which are sequentially stacked on the substrate, and each of which is a silicon-containing inorganic layer.