公开(公告)号：US11901297B2

公开(公告)日：2024-02-13

申请号：US18153028

申请日：2023-01-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yonghyeok Son ,  Junwoo Lee ,  Sungdong Cho

IPC: H01L23/535 ,  H01L21/768 ,  H10B12/00

CPC classification number: H01L23/535 ,  H01L21/76805 ,  H01L21/76843 ,  H01L21/76895 ,  H10B12/0335 ,  H10B12/053 ,  H10B12/09 ,  H10B12/315 ,  H10B12/34 ,  H10B12/482 ,  H10B12/485 ,  H10B12/50

Abstract: A semiconductor memory device includes a substrate including a cell area and a peripheral area, a plurality of capacitors including a plurality of lower electrodes arranged in the cell area, a plurality of capacitor dielectric layers covering the plurality of lower electrodes, and an upper electrode on the plurality of capacitor dielectric layers, an etch stop layer covering the upper electrode, a filling insulation layer covering the etch stop layer and arranged in the cell area and the peripheral area, a plurality of wiring lines on the filling insulation layer, and a first wiring contact plug electrically connecting at least one of the plurality of wiring lines to the upper electrode. The upper electrode includes a first upper electrode layer covering the plurality of capacitor dielectric layers and including a semiconductor material and a second upper electrode layer covering the first upper electrode layer and including a metallic material.

公开(公告)号：US20250142814A1

公开(公告)日：2025-05-01

申请号：US18667445

申请日：2024-05-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yonghyeok Son ,  Jeongil Seo ,  Donghun Lee ,  Seungmo Kang ,  Seung Joo Lee ,  Yujin Cho ,  Seongjun Choi

IPC: H10B12/00

Abstract: A semiconductor device includes an interconnection line, an insulating layer on the interconnection line and having an opening exposing a top surface of the interconnection line, and a redistribution pattern extending into the opening and electrically connected to the interconnection line at a bottom surface of the opening. The interconnection line is configured to provide a current path in a first direction in a region adjacent to the redistribution pattern. The opening comprises a first side surface facing the first direction. A corner region of the opening protrudes away from or is recessed towards the opening at an end portion of the first side surface of the opening when viewed in plan view.

公开(公告)号：US12183680B2

公开(公告)日：2024-12-31

申请号：US18191418

申请日：2023-03-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yonghyeok Son ,  Junwoo Lee ,  Sungdong Cho

IPC: H01L23/535 ,  H01L21/768 ,  H10B12/00

Abstract: A semiconductor memory device includes a substrate including a cell area and a peripheral area, a plurality of capacitors including a plurality of lower electrodes arranged in the cell area, a plurality of capacitor dielectric layers covering the plurality of lower electrodes, and an upper electrode on the plurality of capacitor dielectric layers, an etch stop layer covering the upper electrode, a filling insulation layer covering the etch stop layer and arranged in the cell area and the peripheral area, a plurality of wiring lines on the filling insulation layer, and a first wiring contact plug electrically connecting at least one of the plurality of wiring lines to the upper electrode. The upper electrode includes a first upper electrode layer covering the plurality of capacitor dielectric layers and including a semiconductor material and a second upper electrode layer covering the first upper electrode layer and including a metallic material.

公开(公告)号：US20230238331A1

公开(公告)日：2023-07-27

申请号：US18191418

申请日：2023-03-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yonghyeok Son ,  Junwoo Lee ,  Sungdong Cho

IPC: H01L23/535 ,  H01L21/768 ,  H10B12/00

CPC classification number: H01L23/535 ,  H01L21/76805 ,  H10B12/485 ,  H01L21/76843 ,  H10B12/34 ,  H10B12/315 ,  H10B12/50 ,  H10B12/482 ,  H01L21/76895 ,  H10B12/0335 ,  H10B12/09 ,  H10B12/053

Abstract: A semiconductor memory device includes a substrate including a cell area and a peripheral area, a plurality of capacitors including a plurality of lower electrodes arranged in the cell area, a plurality of capacitor dielectric layers covering the plurality of lower electrodes, and an upper electrode on the plurality of capacitor dielectric layers, an etch stop layer covering the upper electrode, a filling insulation layer covering the etch stop layer and arranged in the cell area and the peripheral area, a plurality of wiring lines on the filling insulation layer, and a first wiring contact plug electrically connecting at least one of the plurality of wiring lines to the upper electrode. The upper electrode includes a first upper electrode layer covering the plurality of capacitor dielectric layers and including a semiconductor material and a second upper electrode layer covering the first upper electrode layer and including a metallic material.

公开(公告)号：US11569171B2

公开(公告)日：2023-01-31

申请号：US17330795

申请日：2021-05-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yonghyeok Son ,  Junwoo Lee ,  Sungdong Cho

IPC: H01L27/108 ,  H01L21/768 ,  H01L23/535

Abstract: A semiconductor memory device includes a substrate including a cell area and a peripheral area, a plurality of capacitors including a plurality of lower electrodes arranged in the cell area, a plurality of capacitor dielectric layers covering the plurality of lower electrodes, and an upper electrode on the plurality of capacitor dielectric layers, an etch stop layer covering the upper electrode, a filling insulation layer covering the etch stop layer and arranged in the cell area and the peripheral area, a plurality of wiring lines on the filling insulation layer, and a first wiring contact plug electrically connecting at least one of the plurality of wiring lines to the upper electrode. The upper electrode includes a first upper electrode layer covering the plurality of capacitor dielectric layers and including a semiconductor material and a second upper electrode layer covering the first upper electrode layer and including a metallic material.