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公开(公告)号:US11217667B2
公开(公告)日:2022-01-04
申请号:US16806629
申请日:2020-03-02
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Seokhoon Kim , Dongmyoung Kim , Kanghun Moon , Hyunkwan Yu , Sanggil Lee , Seunghun Lee , Sihyung Lee , Choeun Lee , Edward Namkyu Cho , Yang Xu
IPC: H01L29/08 , H01L29/78 , H01L27/088 , H01L29/06
Abstract: A semiconductor device includes a substrate, a fin structure on the substrate, a gate structure on the fin structure, a gate spacer on at least on side surface of the gate structure, and a source/drain structure on the fin structure, wherein a topmost portion of a bottom surface of the gate spacer is lower than a topmost portion of a top surface of the fin structure, and a topmost portion of a top surface of the source/drain structure is lower than the topmost portion of the top surface of the fin structure.
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公开(公告)号:US11069776B2
公开(公告)日:2021-07-20
申请号:US16789498
申请日:2020-02-13
Applicant: Samsung Electronics Co., Ltd.
Inventor: Sanggil Lee , Namkyu Cho , Seokhoon Kim , Kang Hun Moon , Hyun-Kwan Yu , Sihyung Lee
IPC: H01L29/08 , H01L29/06 , H01L29/78 , H01L29/66 , H01L21/762
Abstract: Disclosed is a semiconductor device including a first active pattern that extends in a first direction on an active region of a substrate, a first source/drain pattern in a recess on an upper portion of the first active pattern, a gate electrode that runs across a first channel pattern on the upper portion of the first active pattern and extends in a second direction intersecting the first direction, and an active contact electrically connected to the first source/drain pattern.
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公开(公告)号:US11569350B2
公开(公告)日:2023-01-31
申请号:US17371858
申请日:2021-07-09
Applicant: Samsung Electronics Co., Ltd.
Inventor: Sanggil Lee , Namkyu Cho , Seokhoon Kim , Kang Hun Moon , Hyun-Kwan Yu , Sihyung Lee
IPC: H01L29/08 , H01L29/06 , H01L29/78 , H01L29/66 , H01L21/762
Abstract: Disclosed is a semiconductor device including a first active pattern that extends in a first direction on an active region of a substrate, a first source/drain pattern in a recess on an upper portion of the first active pattern, a gate electrode that runs across a first channel pattern on the upper portion of the first active pattern and extends in a second direction intersecting the first direction, and an active contact electrically connected to the first source/drain pattern.
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公开(公告)号:US20190181225A1
公开(公告)日:2019-06-13
申请号:US16138064
申请日:2018-09-21
Applicant: Samsung Electronics Co., Ltd.
Inventor: Choeun Lee , Seokhoon Kim , Sanggil Lee , Seung Hun LEE , Min-Hee Choi
IPC: H01L29/08 , H01L29/10 , H01L29/165 , H01L29/04 , H01L27/11 , H01L29/78 , H01L29/06 , H01L21/8238 , H01L21/308 , H01L21/02 , H01L29/66
Abstract: Disclosed is a semiconductor device that comprises a substrate including a first active pattern vertically protruding from a top surface of the substrate, and a first source/drain pattern filing a first recess formed on an upper portion of the first active pattern. The first source/drain pattern comprises a first semiconductor pattern and a second semiconductor pattern on the first semiconductor pattern. The first semiconductor pattern has a first face, a second face, and a first corner edge defined when the first face and the second face meet with each other. The second semiconductor pattern covers the first face and the second face of the first semiconductor pattern and exposes the first corner edge.
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公开(公告)号:US11735632B2
公开(公告)日:2023-08-22
申请号:US17546690
申请日:2021-12-09
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Seokhoon Kim , Dongmyoung Kim , Kanghun Moon , Hyunkwan Yu , Sanggil Lee , Seunghun Lee , Sihyung Lee , Choeun Lee , Edward Namkyu Cho , Yang Xu
IPC: H01L29/08 , H01L29/78 , H01L27/088 , H01L29/06
CPC classification number: H01L29/0847 , H01L27/0886 , H01L29/0653 , H01L29/0673 , H01L29/785 , H01L29/7853
Abstract: A semiconductor device includes a substrate, a fin structure on the substrate, a gate structure on the fin structure, a gate spacer on at least on side surface of the gate structure, and a source/drain structure on the fin structure, wherein a topmost portion of a bottom surface of the gate spacer is lower than a topmost portion of a top surface of the fin structure, and a topmost portion of a top surface of the source/drain structure is lower than the topmost portion of the top surface of the fin structure.
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公开(公告)号:US20230215867A1
公开(公告)日:2023-07-06
申请号:US17966472
申请日:2022-10-14
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Namkyu CHO , Seokhoon Kim , Sanggil Lee , Pankwi Park
IPC: H01L27/092 , H01L29/06 , H01L29/08 , H01L29/161 , H01L29/423 , H01L29/775 , H01L21/02 , H01L21/8238 , H01L29/66
CPC classification number: H01L27/092 , H01L29/0673 , H01L29/0847 , H01L29/161 , H01L29/42392 , H01L29/775 , H01L21/02603 , H01L21/823807 , H01L21/823814 , H01L29/66545 , H01L29/66742 , H01L29/66439
Abstract: A semiconductor device includes a substrate including a first region, a second region, and active regions extending in a first direction in the first region and in the second region; gate electrodes on the first region and the second region, the gate electrodes intersecting the active regions and extending in a second direction; a plurality of channel layers spaced apart from each other in a third direction on active regions of the active regions and encompassed by the gate electrodes, the third direction being perpendicular to an upper surface of the substrate; and first source/drain regions and second source/drain regions in portions of the active regions that are recessed on both sides of the gate electrodes, the first source/drain regions and the second source/drain regions being connected to the plurality of channel layers, wherein the first source/drain regions are in the first region, and the second source/drain regions are in the second region, wherein an end portion of each of the first source/drain regions in the second direction in a plan view includes a tip region protruding in the second direction, and wherein an end portion of each of the second source/drain regions in the second direction in the plan view extends flatly in the first direction.
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公开(公告)号:US20230141852A1
公开(公告)日:2023-05-11
申请号:US17866966
申请日:2022-07-18
Applicant: Samsung Electronics Co., Ltd.
Inventor: Sanggil Lee , Jungtaek Kim , Dohyun Go , Pankwi Park , Dongsuk Shin , Namkyu Cho , Ryong Ha , Yang Xu
IPC: H01L29/78 , H01L29/08 , H01L21/8238 , H01L27/092
CPC classification number: H01L29/7848 , H01L29/0847 , H01L21/823814 , H01L27/0922
Abstract: A semiconductor device includes a semiconductor active region having a vertical stack of multiple spaced-apart semiconductor channel regions thereon. A gate electrode extends on the active region and between the spaced-apart channel regions. A source/drain region contacts the spaced-apart channel regions. The source/drain region includes a stack of at least first, second and third epitaxial layers having different electrical characteristics. The first epitaxial layer contacts the active region and each of the spaced-apart channel regions. The second epitaxial layer contacts a first portion of an upper surface of the first epitaxial layer. The third epitaxial layer contacts a second portion of the upper surface of the first epitaxial layer. Each of the first, second and third epitaxial layers includes silicon germanium (SiGe) with unequal levels of germanium (Ge) therein. A level of germanium in the third epitaxial layer exceeds a level of germanium in the second epitaxial layer, which exceeds a level of germanium in the first epitaxial layer.
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公开(公告)号:US12062662B2
公开(公告)日:2024-08-13
申请号:US18142210
申请日:2023-05-02
Applicant: Samsung Electronics Co., Ltd.
Inventor: Yang Xu , Hyunkwan Yu , Namkyu Cho , Dongmyoung Kim , Kanghun Moon , Sanggil Lee , Sihyung Lee
IPC: H01L27/092 , H01L29/78
CPC classification number: H01L27/0924 , H01L29/7851
Abstract: A semiconductor device includes a plurality of active fins extending in a first direction, and spaced apart from each other in a second direction, the plurality of active fins having upper surfaces of different respective heights, a gate structure extending in the second across the plurality of active fins, a device isolation film on the substrate, a source/drain region on the plurality of active fins, and including an epitaxial layer on the plurality of active fins, an insulating spacer on an upper surface of the device isolation film and having a lateral asymmetry with respect to a center line of the source/drain region in a cross section taken along the second direction, an interlayer insulating region on the device isolation film and on the gate structure and the source/drain region, and a contact structure in the interlayer insulating region and electrically connected to the source/drain region.
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公开(公告)号:US20230275091A1
公开(公告)日:2023-08-31
申请号:US18142210
申请日:2023-05-02
Applicant: Samsung Electronics Co., Ltd.
Inventor: Yang Xu , Hyunkwan Yu , Namkyu Cho , Dongmyoung Kim , Kanghun Moon , Sanggil Lee , Sihyung Lee
IPC: H01L27/092 , H01L29/78
CPC classification number: H01L27/0924 , H01L29/7851
Abstract: A semiconductor device includes a plurality of active fins extending in a first direction, and spaced apart from each other in a second direction, the plurality of active fins having upper surfaces of different respective heights, a gate structure extending in the second across the plurality of active fins, a device isolation film on the substrate, a source/drain region on the plurality of active fins, and including an epitaxial layer on the plurality of active fins, an insulating spacer on an upper surface of the device isolation film and having a lateral asymmetry with respect to a center line of the source/drain region in a cross section taken along the second direction, an interlayer insulating region on the device isolation film and on the gate structure and the source/drain region, and a contact structure in the interlayer insulating region and electrically connected to the source/drain region.
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公开(公告)号:US20220115375A1
公开(公告)日:2022-04-14
申请号:US17348962
申请日:2021-06-16
Applicant: Samsung Electronics Co., Ltd.
Inventor: Yang Xu , Hyunkwan Yu , Namkyu Cho , Dongmyoung Kim , Kanghun Moon , Sanggil Lee , Sihyung Lee
IPC: H01L27/092 , H01L29/78
Abstract: A semiconductor device includes a plurality of active fins extending in a first direction, and spaced apart from each other in a second direction, the plurality of active fins having upper surfaces of different respective heights, a gate structure extending in the second across the plurality of active fins, a device isolation film on the substrate, a source/drain region on the plurality of active fins, and including an epitaxial layer on the plurality of active fins, an insulating spacer on an upper surface of the device isolation film and having a lateral asymmetry with respect to a center line of the source/drain region in a cross section taken along the second direction, an interlayer insulating region on the device isolation film and on the gate structure and the source/drain region, and a contact structure in the interlayer insulating region and electrically connected to the source/drain region.
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