Semiconductor device including air gap regions below source/drain regions

    公开(公告)号:US12268022B2

    公开(公告)日:2025-04-01

    申请号:US17714695

    申请日:2022-04-06

    Abstract: A semiconductor device includes a substrate having an active region extending in a first direction; a gate structure disposed on the substrate, intersecting the active region, and extending in a second direction; channel layers disposed on the active region to be spaced apart from each other in a third direction, perpendicular to an upper surface of the substrate, and to be surrounded by the gate structure; source/drain regions disposed on both sides of the gate structure and connected to the channel layers; air gap regions located between the source/drain regions and the active region and spaced apart from each other in the third direction; and semiconductor layers alternately disposed with the air gap regions in the third direction and defining the air gap regions, wherein lower ends of the source/drain regions are located on a level lower than an uppermost air gap region.

    SEMICONDUCTOR DEVICE INCLUDING A FIELD EFFECT TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME

    公开(公告)号:US20230059169A1

    公开(公告)日:2023-02-23

    申请号:US17718795

    申请日:2022-04-12

    Abstract: A semiconductor device includes: an active pattern disposed on a substrate; a source/drain pattern disposed on the active pattern; a channel pattern connected to the source/drain pattern, wherein the channel pattern includes semiconductor patterns stacked on each other and spaced apart from each other; and a gate electrode disposed on the channel pattern and extending in a first direction, wherein the gate electrode includes: a channel neighboring part adjacent to a first sidewall of a first semiconductor pattern of the stacked semiconductor patterns; and a body part spaced apart from the first semiconductor pattern, wherein the channel neighboring part is disposed between the body part and the first semiconductor pattern, wherein the first sidewall of the first semiconductor pattern has a first width, wherein the channel neighboring part has a second width less than the first width. The body part has a third width greater than the second width.

    METHOD AND DEVICE FOR SELECTIVE USER PLANE SECURITY IN WIRELESS COMMUNICATION SYSTEM

    公开(公告)号:US20230145440A1

    公开(公告)日:2023-05-11

    申请号:US18092690

    申请日:2023-01-03

    CPC classification number: H04W12/033

    Abstract: An example security processing method includes receiving data packets at a packet data convergence protocol (PDCP) layer from an upper layer and parsing header information of each of the data packets to determine a length of each of the plurality of headers within the corresponding header information and whether a security header is present or absent in the corresponding data packets. The method further includes identifying corresponding header information of the data packets in which the security header is present based on the determination. The method further includes encrypting, based on the determined header lengths, only each of the plurality of headers of the identified corresponding header information in which the security header is present, and thereafter transmitting the one or more data packets to a lower layer after adding information regarding each of the encrypted headers along with their encryption length into a PDCP header.

    Semiconductor devices
    7.
    发明授权

    公开(公告)号:US11670638B2

    公开(公告)日:2023-06-06

    申请号:US17348962

    申请日:2021-06-16

    CPC classification number: H01L27/0924 H01L29/7851

    Abstract: A semiconductor device includes a plurality of active fins extending in a first direction, and spaced apart from each other in a second direction, the plurality of active fins having upper surfaces of different respective heights, a gate structure extending in the second across the plurality of active fins, a device isolation film on the substrate, a source/drain region on the plurality of active fins, and including an epitaxial layer on the plurality of active fins, an insulating spacer on an upper surface of the device isolation film and having a lateral asymmetry with respect to a center line of the source/drain region in a cross section taken along the second direction, an interlayer insulating region on the device isolation film and on the gate structure and the source/drain region, and a contact structure in the interlayer insulating region and electrically connected to the source/drain region.

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