公开(公告)号：US11594550B2

公开(公告)日：2023-02-28

申请号：US16852907

申请日：2020-04-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kang Min Kim ,  Seung Min Song ,  Jae Hoon Shin ,  Joong Shik Shin ,  Geun Won Lim

IPC: H01L27/11582 ,  H01L27/11573 ,  H01L23/528 ,  H01L21/311 ,  H01L27/11565

Abstract: A nonvolatile memory device with improved product reliability and a method of fabricating the same is provided. The nonvolatile memory device comprises a substrate, a first mold structure disposed on the substrate and including a plurality of first gate electrodes, a second mold structure disposed on the first mold structure and including a plurality of second gate electrodes and a plurality of channel structures intersecting the first gate electrodes and the second gate electrodes by penetrating the first and second mold structures, wherein the first mold structure includes first and second stacks, which are spaced apart from each other, and the second mold structure includes a third stack, which is stacked on the first stack, a fourth stack, which is stacked on the second stack, and first connecting parts, which connect the third and fourth stacks.

公开(公告)号：US11121148B2

公开(公告)日：2021-09-14

申请号：US16912894

申请日：2020-06-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kang Min Kim ,  Jin Hyuk Kim ,  Jung Tae Sung ,  Joong Shik Shin ,  Sung Hyung Lee

IPC: H01L27/11578 ,  H01L29/06 ,  H01L29/08 ,  G11C7/18

Abstract: A semiconductor device includes a first substrate including a cell region and surrounded by an extension region, a common source plate on the first substrate, a supporter on the common source plate, a first stack structure on the supporter and including an alternately stacked first insulating film and first gate electrode, a channel hole penetrating the first stack structure, the supporter, and the common source plate on the cell region, and an electrode isolation trench spaced apart from the channel hole in a first direction on the cell region, extending in a second direction, and penetrating the first stack structure, the supporter, and the common source plate, wherein a first thickness of the supporter in a first region adjacent to the electrode isolation trench is greater than a second thickness of the supporter in a second region formed between the electrode isolation trench and the channel hole.

公开(公告)号：US12199043B2

公开(公告)日：2025-01-14

申请号：US17412408

申请日：2021-08-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Geun Won Lim ,  Beyoung Hyun Koh ,  Yong Jin Kwon ,  Joong Shik Shin

IPC: H01L23/535 ,  H01L21/768 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11582 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27 ,  H10B43/40

Abstract: A semiconductor memory device may include a mold structure that includes mold insulation films and gate electrodes alternately stacked on a first substrate, a channel structure that penetrates the mold structure and intersects the gate electrodes, a block separation region that extends in a first direction parallel to an upper surface of the first substrate and cuts the mold structure, a first dam region and a second dam region spaced apart from each other, that each having a closed loop in a plan view and each cutting the mold structure, pad insulation films in the first and second dam regions that are alternately stacked with the mold insulation films and include a material different from the mold insulation films, and a through via which penetrates through the first substrate, the mold insulation films, and the pad insulation films, in the first dam region but not in the second dam region.

公开(公告)号：US11723200B2

公开(公告)日：2023-08-08

申请号：US17399239

申请日：2021-08-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kang Min Kim ,  Jin Hyuk Kim ,  Jung Tae Sung ,  Joong Shik Shin ,  Sung Hyung Lee

IPC: H10B43/20 ,  H01L29/06 ,  H01L29/08 ,  G11C7/18

CPC classification number: H10B43/20 ,  G11C7/18 ,  H01L29/0649 ,  H01L29/0847

Abstract: A semiconductor device includes a first substrate including a cell region and surrounded by an extension region, a common source plate on the first substrate, a supporter on the common source plate, a first stack structure on the supporter and including an alternately stacked first insulating film and first gate electrode, a channel hole penetrating the first stack structure, the supporter, and the common source plate on the cell region, and an electrode isolation trench spaced apart from the channel hole in a first direction on the cell region, extending in a second direction, and penetrating the first stack structure, the supporter, and the common source plate, wherein a first thickness of the supporter in a first region adjacent to the electrode isolation trench is greater than a second thickness of the supporter in a second region formed between the electrode isolation trench and the channel hole.

公开(公告)号：US20190355740A1

公开(公告)日：2019-11-21

申请号：US16192232

申请日：2018-11-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang Jun Hong ,  Ee Jou Kim ,  Joong Shik Shin

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/11573 ,  H01L29/792 ,  H01L21/768

Abstract: A semiconductor device comprises a lower conductive layer on a substrate. A conductive line is on the lower conductive layer. A buried trench in the conductive line is provided. A supporter which is on the conductive line and extends in the buried trench is provided. A stack structure including a plurality of insulating layers and a plurality of conductive layers that are alternately stacked is on the supporter. A channel structure passing through the stack structure, the supporter, and the conductive line is provided. An isolation trench passing through the stack structure, the supporter, and the conductive line is provided.

公开(公告)号：US11114463B2

公开(公告)日：2021-09-07

申请号：US16892384

申请日：2020-06-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seung Jun Shin ,  Hyun Mog Park ,  Joong Shik Shin

IPC: H01L27/11582 ,  H01L27/11575 ,  H01L27/11565 ,  H01L27/11526 ,  H01L27/11573 ,  H01L27/11556 ,  H01L21/3213 ,  H01L29/792 ,  H01L29/78 ,  H01L29/66 ,  H01L29/417 ,  H01L21/768 ,  H01L29/788 ,  H01L27/1157

Abstract: A semiconductor device includes gate electrodes stacked along a direction perpendicular to an upper surface of a substrate, the gate electrodes extending to different lengths in a first direction, and each gate electrode including subgate electrodes spaced apart from each other in a second direction perpendicular to the first direction, and gate connection portions connecting subgate electrodes of a same gate electrode of the gate electrodes to each other, channels extending through the gate electrodes perpendicularly to the upper surface of the substrate, and dummy channels extending through the gate electrodes perpendicularly to the upper surface of the substrate, the dummy channels including first dummy channels arranged in rows and columns, and second dummy channels arranged between the first dummy channels in a region including the gate connection portions.

公开(公告)号：US20200235124A1

公开(公告)日：2020-07-23

申请号：US16843460

申请日：2020-04-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang Jun Hong ,  Ee Jou Kim ,  Joong Shik Shin

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L21/768 ,  H01L29/792 ,  H01L27/11573 ,  H01L27/11551 ,  H01L27/11524 ,  H01L27/11529

Abstract: A semiconductor device comprises a lower conductive layer on a substrate. A conductive line is on the lower conductive layer. A buried trench in the conductive line is provided. A supporter which is on the conductive line and extends in the buried trench is provided. A stack structure including a plurality of insulating layers and a plurality of conductive layers that are alternately stacked is on the supporter. A channel structure passing through the stack structure, the supporter, and the conductive line is provided. An isolation trench passing through the stack structure, the supporter, and the conductive line is provided.

公开(公告)号：US10515819B2

公开(公告)日：2019-12-24

申请号：US15844681

申请日：2017-12-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji Hoon Park ,  Joong Shik Shin ,  Byoung Il Lee ,  Jong Ho Woo ,  Eun Taek Jung ,  Jun Ho Cha

IPC: H01L27/11531 ,  H01L21/3105 ,  H01L21/763 ,  H01L21/28 ,  H01L21/8238 ,  H01L27/11573 ,  H01L27/11592 ,  H01L21/762 ,  H01L21/311

Abstract: A semiconductor device includes a substrate having a first region and a second region, the first region including memory cells, and the second region including transistors for driving the memory cells, and device isolation regions disposed within the substrate to define active regions of the substrate. The active regions include a first guard active region surrounding the first region, a second guard active region surrounding a portion of the second region, and at least one dummy active region disposed between the first guard active region and the second guard active region.

公开(公告)号：US20250105155A1

公开(公告)日：2025-03-27

申请号：US18976693

申请日：2024-12-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Geun Won Lim ,  Beyoung Hyun Koh ,  Yong Jin Kwon ,  Joong Shik Shin

IPC: H01L23/535 ,  H01L21/768 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27 ,  H10B43/40

Abstract: A semiconductor memory device may include a mold structure that includes mold insulation films and gate electrodes alternately stacked on a first substrate, a channel structure that penetrates the mold structure and intersects the gate electrodes, a block separation region that extends in a first direction parallel to an upper surface of the first substrate and cuts the mold structure, a first dam region and a second dam region spaced apart from each other, that each having a closed loop in a plan view and each cutting the mold structure, pad insulation films in the first and second dam regions that are alternately stacked with the mold insulation films and include a material different from the mold insulation films, and a through via which penetrates through the first substrate, the mold insulation films, and the pad insulation films, in the first dam region but not in the second dam region.

公开(公告)号：US12035528B2

公开(公告)日：2024-07-09

申请号：US17394499

申请日：2021-08-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seung Jun Shin ,  Hyun Mog Park ,  Joong Shik Shin

IPC: H10B43/27 ,  H01L21/3213 ,  H01L21/768 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  H10B41/27 ,  H10B41/40 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40 ,  H10B43/50

CPC classification number: H10B43/27 ,  H01L21/3213 ,  H01L21/76802 ,  H01L21/76877 ,  H01L29/41775 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/7889 ,  H01L29/7926 ,  H10B41/27 ,  H10B41/40 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40 ,  H10B43/50

Abstract: A semiconductor device includes gate electrodes stacked along a direction perpendicular to an upper surface of a substrate, the gate electrodes extending to different lengths in a first direction, and each gate electrode including subgate electrodes spaced apart from each other in a second direction perpendicular to the first direction, and gate connection portions connecting subgate electrodes of a same gate electrode of the gate electrodes to each other, channels extending through the gate electrodes perpendicularly to the upper surface of the substrate, and dummy channels extending through the gate electrodes perpendicularly to the upper surface of the substrate, the dummy channels including first dummy channels arranged in rows and columns, and second dummy channels arranged between the first dummy channels in a region including the gate connection portions.