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    METHOD OF DETECTING FAILURE OF A SEMICONDUCTOR DEVICE
    1.
    发明申请
    METHOD OF DETECTING FAILURE OF A SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20190385918A1

    公开(公告)日：2019-12-19

    申请号：US16245686

    申请日：2019-01-11

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Ji-Young CHOI ,  Zhan ZHAN ,  Min-Seob KIM ,  Ju-Hyun KIM ,  Sung-Gun KANG ,  Hwa-Sung RHEE

    IPC: H01L21/66 ,  G01R31/26

    Abstract: A method of detecting failure of a semiconductor device includes forming an active fin on an active region of a substrate, the active fin extending in a first direction, forming a gate structure on the active fin, the gate structure extending in a second direction intersecting the first direction, forming source/drain layers on respective portions of the active fins at opposite sides of the gate structure, forming a wiring to be electrically connected to the source/drain layers, and applying a voltage to measure a leakage current between the source/drain layers. Only one or two active fins may be formed on the active region. Only one or two gate structures may be formed on the active fin.

    SEMICONDUCTOR DEVICE
    2.
    发明申请
    SEMICONDUCTOR DEVICE 审中-公开
    半导体器件

    公开(公告)号：US20160372467A1

    公开(公告)日：2016-12-22

    申请号：US15014291

    申请日：2016-02-03

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Ju-Youn KIM ,  Hyun-Jo KIM ,  Hwa-Sung RHEE

    IPC: H01L27/088 ,  H01L29/06 ,  H01L27/02

    CPC classification number: H01L27/0886 ,  H01L27/0207 ,  H01L29/0649

    Abstract: Semiconductor devices are provided. The semiconductor device includes an active fin which extends along a first direction and has a protruding shape, a gate structure which is disposed on the active fin to extend along a second direction intersecting the first direction, and a spacer which is disposed on at least one side of the gate structure, wherein the gate structure includes a first area and a second area which is adjacent to the first area in the second direction, wherein a first width of the first area in the first direction is different from a second width of the second area in the first direction, and the spacer extends continuously along both the first area and the second area.

    Abstract translation: 提供半导体器件。 该半导体器件包括沿着第一方向延伸并具有突出形状的有源鳍片，设置在有源鳍片上以沿与第一方向相交的第二方向延伸的栅极结构，以及设置在至少一个 所述栅极结构包括第一区域和与所述第二方向上的所述第一区域相邻的第二区域，其中，所述第一方向上的所述第一区域的第一宽度不同于所述第一区域的第二宽度， 第二区域沿着第一方向延伸，并且间隔件沿着第一区域和第二区域连续地延伸。

    TEST PATTERN OF SEMICONDUCTOR DEVICE
    3.
    发明申请
    TEST PATTERN OF SEMICONDUCTOR DEVICE 有权
    半导体器件的测试图案

    公开(公告)号：US20150162331A1

    公开(公告)日：2015-06-11

    申请号：US14326471

    申请日：2014-07-09

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Dae-Lim KANG ,  Min-Ho KWON ,  Wei-Hua HSU ,  Sang-Hyun WOO ,  Hwa-Sung RHEE ,  Jun-Suk CHOI

    IPC: H01L27/088 ,  H01L21/66

    CPC classification number: H01L22/34 ,  H01L27/0886

    Abstract: A test pattern of a semiconductor device is provided, which includes first and second fins formed to project from a substrate and arranged to be spaced apart from each other, first and second gate structures formed to cross the first and second fins, respectively, a first source region and a first drain region arranged on the first fin on one side and the other side of the first gate structure, a second source region and a second drain region arranged on the second fin on one side and the other side of the second gate structure, a first conductive pattern connected to the first and second drain regions to apply a first voltage to the first and second drain regions and a second conductive pattern connecting the first source region and the second gate structure to each other.

    Abstract translation: 提供了一种半导体器件的测试图案，其包括形成为从衬底突出并布置成彼此间隔开的第一和第二鳍片，分别形成为跨越第一和第二鳍片的第一和第二栅极结构，第一和第二鳍片 源极区域和布置在第一鳍片的第一栅极结构的一侧和另一侧上的第一漏极区域，在第二栅极的一侧和另一侧上布置在第二鳍片上的第二源极区域和第二漏极区域 结构，连接到第一和第二漏极区域以将第一电压施加到第一和第二漏极区域的第一导电图案以及将第一源极区域和第二栅极结构彼此连接的第二导电图案。

    SEMICONDUCTOR DEVICE
    4.
    发明申请
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20190221564A1

    公开(公告)日：2019-07-18

    申请号：US16366140

    申请日：2019-03-27

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Ju-Youn KIM ,  Hyun-Jo KIM ,  Hwa-Sung RHEE

    IPC: H01L27/088 ,  H01L29/78 ,  H01L27/02 ,  H01L29/06 ,  H01L29/66

    CPC classification number: H01L27/0886 ,  H01L27/0207 ,  H01L29/0649 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7856

    Abstract: Semiconductor devices are provided. The semiconductor device includes an active fin which extends along a first direction and has a protruding shape, a gate structure which is disposed on the active fin to extend along a second direction intersecting the first direction, and a spacer which is disposed on at least one side of the gate structure, wherein the gate structure includes a first area and a second area which is adjacent to the first area in the second direction, wherein a first width of the first area in the first direction is different from a second width of the second area in the first direction, and the spacer extends continuously along both the first area and the second area.

    SEMICONDUCTOR DEVICE COMPRISING CAPACITOR AND METHOD OF MANUFACTURING THE SAME
    6.
    发明申请
    SEMICONDUCTOR DEVICE COMPRISING CAPACITOR AND METHOD OF MANUFACTURING THE SAME 有权
    包含电容器的半导体器件及其制造方法

    公开(公告)号：US20150061073A1

    公开(公告)日：2015-03-05

    申请号：US14245079

    申请日：2014-04-04

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Yoon-Hae KIM ,  Hwa-Sung RHEE

    IPC: H01L49/02 ,  H01L23/522

    CPC classification number: H01L27/016 ,  H01L21/76879 ,  H01L23/5223 ,  H01L23/5228 ,  H01L27/10852 ,  H01L27/10858 ,  H01L27/10861 ,  H01L28/20 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A semiconductor device includes an interlayer dielectric layer on a substrate, the interlayer dielectric layer having an upper surface, a lower plug extending down into the interlayer dielectric layer from the upper surface of the interlayer dielectric layer, the lower plug having an upper surface, a first dielectric layer pattern on the upper surface of the lower plug, at least a portion of the first dielectric layer pattern being directly connected to the upper surface of the lower plug, a first metal electrode pattern on the first dielectric layer pattern, a first upper plug electrically connected to the first metal electrode pattern, and a second upper plug on the lower plug, the second upper plug being spaced apart from the first upper plug.

    Abstract translation: 半导体器件包括在衬底上的层间电介质层，层间绝缘层具有上表面，下电极从层间电介质层的上表面向下延伸到层间电介质层中，下插塞具有上表面， 第一电介质层图案在下塞子的上表面上，第一介电层图案的至少一部分直接连接到下塞子的上表面，第一介电层图案上的第一金属电极图案，第一上层 电插头与第一金属电极图形电连接，第二上插头位于下插头上，第二上插头与第一上插头间隔开。

    SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
    7.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME 审中-公开
    半导体器件及其制造方法

    公开(公告)号：US20140374827A1

    公开(公告)日：2014-12-25

    申请号：US14259212

    申请日：2014-04-23

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Dong-Chan SUH ,  Chung-Geun KOH ,  Seong-Hoon JEONG ,  Kwan-Heum LEE ,  Hwa-Sung RHEE ,  Gyeom KIM

    IPC: H01L29/78 ,  H01L29/06

    CPC classification number: H01L29/785 ,  H01L29/66545

    Abstract: A semiconductor device includes a fin type active pattern protruding above a device isolation layer, a gate electrode on the device isolation layer and intersecting the fin type active pattern, an elevated source/drain on the fin type active pattern at both sides of the gate electrode, and a fin spacer on a side wall of the fin type active pattern, the fin spacer having a low dielectric constant and being between the device isolation layer and the elevated source/drain.

    Abstract translation: 半导体器件包括突出在器件隔离层上方的翅片型有源图案，器件隔离层上的栅电极并与鳍式有源图案相交，栅极电极两侧的翅片型有源图案上的升高的源极/漏极 以及在翅片型有源图案的侧壁上的翅片间隔件，翅片间隔件具有低介电常数并且位于器件隔离层和升高的源极/漏极之间。

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