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    Nonvolatile memory device including multi-plane structure
    2.
    发明授权
    Nonvolatile memory device including multi-plane structure 有权

    公开(公告)号：US10236065B2

    公开(公告)日：2019-03-19

    申请号：US16049863

    申请日：2018-07-31

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Donghun Kwak ,  Daeseok Byeon ,  Chiweon Yoon

    IPC: G11C11/00 ,  G11C16/08 ,  G11C16/04

    Abstract: A nonvolatile memory device includes a memory cell array having a first plane and a second plane and an address decoder connected to the first plane through first string select lines and connected to the second plane through second string select line. The address decoder provides a string select signal and a string unselect signal to the first and second string select lines. The address decoder independently provides the string select signal and the string unselect signal to the first and second string select lines in each plane based on different string select line addresses corresponding to the first and second planes.

    Nonvolatile memory devices, memory systems and related control methods
    4.
    发明授权
    Nonvolatile memory devices, memory systems and related control methods 有权
    非易失存储器件，存储器系统和相关控制方法

    公开(公告)号：US09520168B2

    公开(公告)日：2016-12-13

    申请号：US15151687

    申请日：2016-05-11

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Donghun Kwak ,  Hyun Jun Yoon ,  Dongkyo Shim

    IPC: G11C7/00 ,  G11C5/06 ,  G11C7/22 ,  G11C7/10

    CPC classification number: G11C7/22 ,  G11C7/10 ,  G11C7/1063 ,  G11C16/0483 ,  G11C16/26

    Abstract: A nonvolatile memory device includes a cell array including a plurality of cell strings extending on a substrate in a vertical direction, a page buffer connected to a plurality of bit lines and configured to store sensing data of the cell array in a sensing operation, a voltage generator configured to provide voltages to a plurality of word lines and the plurality of bit lines, and an input/output buffer configured to temporarily store the sensing data received in a data dump from the page buffer and to output the temporarily stored data to an external device. The nonvolatile memory device further includes control logic configured to set a status of the nonvolatile memory device to a ready state after the sensing data is dumped to the input/output buffer and before recovery of the cell array from a bias voltage of the sensing operation is complete.

    Abstract translation: 一种非易失性存储器件，包括一个单元阵列，该单元阵列包括在垂直方向上在基片上延伸的多个单元串，连接到多个位线的一个页缓冲器，并且被配置为在感测操作中存储该单元阵列的感测数据， 发生器，其被配置为向多个字线和所述多个位线提供电压;以及输入/输出缓冲器，被配置为临时存储从所述页缓冲器接收的数据转储中的感测数据，并将所述临时存储的数据输出到外部 设备。 非易失性存储装置还包括控制逻辑，其被配置为在将感测数据转储到输入/输出缓冲器之后并且在从感测操作的偏置电压恢复单元阵列之前将非易失性存储器件的状态设置为就绪状态 完成。

    Nonvolatile memory device and memory system including the same
    7.
    发明授权
    Nonvolatile memory device and memory system including the same 有权
    非易失性存储器件和包括其的存储器系统

    公开(公告)号：US09251904B2

    公开(公告)日：2016-02-02

    申请号：US14458567

    申请日：2014-08-13

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Doohyun Kim ,  Hyun Jun Yoon ,  Donghun Kwak ,  Kitae Park ,  Changyeon Yu

    IPC: G11C29/56 ,  G11C16/26

    CPC classification number: G11C16/26 ,  G11C11/5642 ,  G11C16/3418 ,  G11C16/3495 ,  G11C29/52 ,  G11C29/56

    Abstract: A nonvolatile memory device may include a memory cell array which is arranged in rows and columns and has multi-level memory cells; a voltage generator providing a plurality of read voltages to a selected row of the memory cell array; and control logic performing a plurality of page read operations using the read voltages. A first read voltage and a second read voltage among the plurality of read voltages are each associated with a higher probability of occurrence of a bit read error than at least one other read voltage among the plurality of read voltages. The control logic uses the first read voltage and the second read voltage in different page read operations than each other.

    Abstract translation: 非易失性存储器件可以包括以行和列布置并具有多级存储单元的存储单元阵列; 电压发生器，向存储单元阵列的选定行提供多个读取电压; 以及控制逻辑，使用读取的电压执行多个页面读取操作。 多个读取电压之间的第一读取电压和第二读取电压各自与多个读取电压中的至少一个其他读取电压的比特读取错误的发生概率相关。 控制逻辑在彼此不同的页读操作中使用第一读电压和第二读电压。

    Flash memory system having abnormal wordline detector and abnormal wordline detection method
    8.
    发明授权
    Flash memory system having abnormal wordline detector and abnormal wordline detection method 有权

    公开(公告)号：US10528420B2

    公开(公告)日：2020-01-07

    申请号：US13935604

    申请日：2013-07-05

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Donghun Kwak ,  Sang-Soo Park ,  Jaewoo Im

    IPC: G06F11/10

    Abstract: A flash memory controller for a flash memory system includes an ECC circuit that receives first page data and second page data read from the flash memory, and respectively counts a first number of fail bits in the first page data and a second number of fail bits in the second page data, an abnormal wordline detector configured to compare the first number of fail bits and second number of fail bits to derive a fail bit change rate between the first page data and the second page data, and generate an abnormal wordline detection signal in response to the fail bit change rate, and a control unit that controls operation of the flash memory in response to the abnormal wordline detection signal.

    Nonvolatile memory device with first and second precharge circuit
    9.
    发明授权
    Nonvolatile memory device with first and second precharge circuit 有权

    公开(公告)号：US10102910B2

    公开(公告)日：2018-10-16

    申请号：US15806543

    申请日：2017-11-08

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Ji-Sang Lee ,  Donghun Kwak ,  Daeseok Byeon ,  Chiweon Yoon

    IPC: G11C11/34 ,  G11C16/10 ,  G11C11/56 ,  G11C16/24 ,  G11C16/04 ,  G11C16/26

    Abstract: A nonvolatile memory includes a memory cell array, a row decoder circuit, and a page buffer circuit. The row decoder circuit applies a turn-on voltage to string selection lines, which are connected to string selection transistors of a selected memory block, at a first precharge operation in response to a write command received from an external device. The page buffer circuit applies, in response to the write command, a first voltage to bit lines, which are connected to the string selection transistors, through a first precharge circuit at the first precharge operation regardless of loaded data and applies the first voltage and a second voltage to the bit lines through a second precharge circuit at a second precharge operation based on the loaded data. During the first precharge operation, write data is loaded onto the page buffer circuit.

    Three-dimensional flash memory device including dummy word line
    10.
    发明授权
    Three-dimensional flash memory device including dummy word line 有权
    三维闪存设备包括虚拟字线

    公开(公告)号：US09496038B1

    公开(公告)日：2016-11-15

    申请号：US15091843

    申请日：2016-04-06

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Donghun Kwak ,  Sang-Wan Nam ,  Daeseok Byeon ,  Chiweon Yoon

    IPC: G11C16/04 ,  G11C16/28 ,  G11C16/26

    CPC classification number: G11C16/0483 ,  G11C7/14 ,  G11C8/14 ,  G11C16/08 ,  G11C16/26 ,  G11C16/3418

    Abstract: A three-dimensional flash memory device includes a plurality of cell strings arranged in a direction perpendicular to a substrate. The three-dimensional flash memory includes a first dummy word line disposed between a ground selection line and a main word line, and a second dummy word line disposed between the main word line and a string selection line and being asymmetric with respect to the first dummy word line. Voltages of different levels are respectively applied to the first and second dummy word lines during a read operation.

    Abstract translation: 三维闪速存储器件包括沿垂直于衬底的方向布置的多个单元串。 三维闪存包括设置在地选择线和主字线之间的第一虚拟字线和设置在主字线和字串选择线之间的第二虚拟字线，并且相对于第一伪线不对称 字线。 在读取操作期间，不同电平的电压分别应用于第一和第二伪字线。

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