公开(公告)号：US08941173B2

公开(公告)日：2015-01-27

申请号：US13775586

申请日：2013-02-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seung-Uk Han ,  Jae-Hoon Lee ,  Jun-Su Kim ,  Satoru Yamada ,  Jin-Seong Lee ,  Nam-Ho Jeon

IPC: H01L29/66 ,  H01L27/088 ,  H01L27/11 ,  H01L27/108

CPC classification number: H01L27/088 ,  H01L27/108 ,  H01L27/11

Abstract: According to an example embodiment of inventive concepts, a capacitorless memory device includes a capacitorless memory cell that includes a bit line on a substrate; a read transistor, and a write transistor. The read transistor may include first to third impurity layers stacked in a vertical direction on the bit line. The first and third layers may be a first conductive type, and the second impurity layer may be a second conductive type that differs from the first conductive type. The write transistor may include a source layer, a body layer, and a drain layer stacked in the vertical direction on the substrate, and a gate line that is adjacent to a side surface of the body layer. The gate line may be spaced apart from the side surface of the body layer. The source layer may be adjacent to a side surface of the second impurity layer.

Abstract translation: 根据本发明构思的示例性实施例，一种无电容器存储器件包括：无电容器存储器单元，其在衬底上包括位线; 读取晶体管和写入晶体管。 读取晶体管可以包括在位线上沿垂直方向堆叠的第一至第三杂质层。 第一和第三层可以是第一导电类型，并且第二杂质层可以是不同于第一导电类型的第二导电类型。 写入晶体管可以包括在基板上沿垂直方向堆叠的源极层，主体层和漏极层，以及与主体层的侧表面相邻的栅极线。 栅极线可以与主体层的侧表面间隔开。 源极层可以与第二杂质层的侧表面相邻。

公开(公告)号：US10177253B2

公开(公告)日：2019-01-08

申请号：US15290240

申请日：2016-10-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-Soo Kim ,  Gi-Gwan Park ,  Sang-Koo Kang ,  Koung-Min Ryu ,  Jae-Hoon Lee ,  Tae-Won Ha

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/40 ,  H01L29/423 ,  H01L29/51

Abstract: A semiconductor device capable of adjusting profiles of a gate electrode and a gate spacer by implanting or doping an element semiconductor material into an interlayer insulating layer may be provided. The semiconductor device may include a gate spacer on a substrate, the gate spacer defining a trench, a gate electrode filling the trench, and an interlayer insulating layer on the substrate, which surrounds the gate spacer, and at least a portion of which includes germanium.

公开(公告)号：US20190007057A1

公开(公告)日：2019-01-03

申请号：US16104414

申请日：2018-08-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jae-Hoon Lee ,  Jong-woo Lee ,  Chilun Lo ,  Seung-hyun Oh ,  Jong-mi Lee

IPC: H03M3/00

CPC classification number: H03M3/464 ,  H03M3/426 ,  H03M3/434 ,  H03M3/436 ,  H03M3/498

Abstract: A variable feedback gain delta modulator includes group of capacitors commonly connected to a first terminal and are respectively classified into a first capacitor group and a second capacitor group; a comparator for sequentially generating n-bit digital output signals based on a voltage of the first terminal; and a switch group including switches respectively connected to the capacitors, wherein the switches are respectively classified into a first switch group and a second switch group respectively connected to the first capacitor group and the second capacitor group, and the first switch group and the second switch group respectively operate according to a first control signal and a second control signal that are determined based on the n-bit digital output signals and the variable feedback gain.

公开(公告)号：US20150162443A1

公开(公告)日：2015-06-11

申请号：US14452730

申请日：2014-08-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-Hoon Lee ,  Tae-Geun Kim ,  Chan-Ho Park ,  Hyun-Jung Her

IPC: H01L29/78 ,  H01L27/088

CPC classification number: H01L29/4236 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/1095 ,  H01L29/7397

Abstract: In a semiconductor power device and method of the same, the semiconductor device includes a substrate, a gate electrode structure, first impurity regions, an insulating interlayer, first contact plugs and a first metal pattern. The substrate includes an active region and a termination region. The gate electrode structure includes a first gate electrode and a second gate electrode buried in the substrate, and upper surfaces of the gate electrode structure are lower than an upper surface of the substrate between the first and second gate electrodes. The first impurity regions are formed in the substrate between the first and second electrodes. The insulating interlayer having a flat top surface is formed on the substrate and the gate electrode structure. The first contact plugs are formed through the insulating interlayer, and the first contact plugs contact the first impurity regions. The first metal pattern having a flat top surface is formed on the first contact plugs and the insulating interlayer. Defect of the semiconductor power device may be decreased, and the semiconductor power device may have good electric characteristics.

Abstract translation: 在半导体功率器件及其制造方法中，半导体器件包括衬底，栅电极结构，第一杂质区，绝缘中间层，第一接触插塞和第一金属图案。 衬底包括有源区和端接区。 栅电极结构包括埋在基板中的第一栅极电极和第二栅极电极，栅电极结构的上表面比第一和第二栅电极之间的衬底的上表面低。 在第一和第二电极之间的衬底中形成第一杂质区。 在基板和栅电极结构上形成具有平坦顶面的绝缘中间层。 第一接触插塞通过绝缘中间层形成，并且第一接触插塞接触第一杂质区域。 在第一接触插塞和绝缘中间层上形成具有平坦顶面的第一金属图案。 可以减少半导体功率器件的缺陷，并且半导体功率器件可能具有良好的电特性。

公开(公告)号：US12015086B2

公开(公告)日：2024-06-18

申请号：US17315818

申请日：2021-05-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-Hoon Lee ,  Gi-gwan Park ,  Tae-young Kim

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/15 ,  H01L29/16 ,  H01L29/20 ,  H01L29/22 ,  H01L29/267 ,  H01L29/66

CPC classification number: H01L29/7851 ,  H01L29/0847 ,  H01L29/155 ,  H01L29/1608 ,  H01L29/20 ,  H01L29/2006 ,  H01L29/2206 ,  H01L29/267 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7854

Abstract: A semiconductor device includes a substrate including a fin-shaped active region that protrudes from the substrate, a gate insulating film covering a top surface and both side walls of the fin-shaped active region, a gate electrode on the top surface and the both side walls of the fin-shaped active region and covering the gate insulating film, one pair of insulating spacers on both side walls of the gate electrode, one pair of source/drain region on the fin-shaped active region and located on both sides of the gate electrode, and a lower buffer layer between the fin-shaped active region the source/drain region. The source/drain regions include a compound semiconductor material including atoms from different groups. The lower buffer layer includes a compound semiconductor material that is amorphous and includes atoms from different groups.

公开(公告)号：US08969915B2

公开(公告)日：2015-03-03

申请号：US14338187

申请日：2014-07-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-Hoon Lee ,  Ki-Se Kim

IPC: H01L31/0328 ,  H01L23/373 ,  H01L29/20 ,  H01L29/205

CPC classification number: H01L23/373 ,  H01L23/3731 ,  H01L23/3736 ,  H01L23/3738 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/66462 ,  H01L29/778 ,  H01L29/7787 ,  H01L29/872 ,  H01L2224/13 ,  H01L2924/12032 ,  H01L2924/00

Abstract: Gallium nitride (GaN) based semiconductor devices and methods of manufacturing the same. The GaN-based semiconductor device may include a heterostructure field effect transistor (HFET) or a Schottky diode, arranged on a heat dissipation substrate. The HFET device may include a GaN-based multi-layer having a recess region; a gate arranged in the recess region; and a source and a drain that are arranged on portions of the GaN-based multi-layer at two opposite sides of the gate (or the recess region). The gate, the source, and the drain may be attached to the heat dissipation substrate. The recess region may have a double recess structure. While such a GaN-based semiconductor device is being manufactured, a wafer bonding process and a laser lift-off process may be used.

Abstract translation: 基于氮化镓（GaN）的半导体器件及其制造方法。 GaN基半导体器件可以包括布置在散热衬底上的异质结构场效应晶体管（HFET）或肖特基二极管。 HFET器件可以包括具有凹陷区域的GaN基多层; 设置在所述凹部区域中的栅极; 以及布置在栅极（或凹部区域）的两个相对侧的GaN基多层的部分上的源极和漏极。 栅极，源极和漏极可以附接到散热基板。 凹部区域可以具有双凹槽结构。 虽然正在制造这种GaN基半导体器件，但是可以使用晶片接合工艺和激光剥离工艺。

公开(公告)号：US10580891B2

公开(公告)日：2020-03-03

申请号：US16193521

申请日：2018-11-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-Soo Kim ,  Gi-Gwan Park ,  Sang-Koo Kang ,  Koung-Min Ryu ,  Jae-Hoon Lee ,  Tae-Won Ha

IPC: H01L29/78 ,  H01L29/40 ,  H01L29/423 ,  H01L29/51 ,  H01L29/66

Abstract: A semiconductor device capable of adjusting profiles of a gate electrode and a gate spacer by implanting or doping an element semiconductor material into an interlayer insulating layer may be provided. The semiconductor device may include a gate spacer on a substrate, the gate spacer defining a trench, a gate electrode filling the trench, and an interlayer insulating layer on the substrate, which surrounds the gate spacer, and at least a portion of which includes germanium.

公开(公告)号：US10439636B2

公开(公告)日：2019-10-08

申请号：US16104414

申请日：2018-08-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jae-Hoon Lee ,  Jong-woo Lee ,  Chilun Lo ,  Seung-hyun Oh ,  Jong-mi Lee

IPC: H03M3/00

Abstract: A variable feedback gain delta modulator includes group of capacitors commonly connected to a first terminal and are respectively classified into a first capacitor group and a second capacitor group; a comparator for sequentially generating n-bit digital output signals based on a voltage of the first terminal; and a switch group including switches respectively connected to the capacitors, wherein the switches are respectively classified into a first switch group and a second switch group respectively connected to the first capacitor group and the second capacitor group, and the first switch group and the second switch group respectively operate according to a first control signal and a second control signal that are determined based on the n-bit digital output signals and the variable feedback gain.

公开(公告)号：US10324629B2

公开(公告)日：2019-06-18

申请号：US15869769

申请日：2018-01-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jong-Hoon Lee ,  Eun-Suk Cho ,  Woo-Pyo Jeong ,  Sang-Wan Nam ,  Jung-Ho Song ,  Yun-Ho Hong ,  Jae-Hoon Lee

IPC: G11C7/06 ,  G06F3/06 ,  H01L27/02 ,  H01L21/265 ,  G11C7/10 ,  G11C16/26 ,  G11C16/04 ,  G11C16/32 ,  H01L27/11582 ,  H01L27/11573

Abstract: A non-volatile memory device includes a memory cell array region in which memory cells are vertically stacked on a substrate and a page buffer region in which first and second page buffers are arranged. A first distance between the memory cell array region and the first page buffer is shorter than a second distance between the memory cell array region and the second page buffer. The first page buffer includes a first transistor driven in response to a first control signal. The second page buffer includes a second transistor driven in response to a second control signal corresponding to the first control signal. At least one of design constraints and processing constraints with respect to the first and second transistors is different.

公开(公告)号：US20190173501A1

公开(公告)日：2019-06-06

申请号：US16203943

申请日：2018-11-29

Applicant: Samsung Electronics Co., LTD.

Inventor： SEUNG-HYUN OH ,  Chilun Lo ,  Barosaim Sung ,  Jae-Hoon Lee ,  Jong-Woo Lee

IPC: H04B1/00 ,  H04L27/26 ,  H03L7/08

Abstract: Provided are a radio-frequency integrated chip (RFIC) and a wireless communication device including the RFIC. An RFIC configured to receive a carrier aggregated receive signal having at least first and second carrier signals may include first and second carrier receivers configured to generate, from the receive signal, first and second digital carrier signals, respectively. A phase-locked loop (PLL) may output a first frequency signal having a first frequency to the first carrier receiver and the second carrier receiver. The first and second carrier receivers may include first and second analog mixers, respectively, for translating frequencies of the receive signal, using the first frequency signal and the second frequency signal, respectively, Each of the first and second carrier receivers may further include a digital mixer for farther translating the frequencies of the receive signal in the digital domain.