公开(公告)号：US09472622B2

公开(公告)日：2016-10-18

申请号：US14263441

申请日：2014-04-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jae-Hoon Lee ,  Tae-Geun Kim ,  Chan-Ho Park ,  Hyun-Jung Her

IPC: H01L29/66 ,  H01L29/10 ,  H01L29/739 ,  H01L29/40 ,  H01L29/06

CPC classification number: H01L29/1095 ,  H01L29/0619 ,  H01L29/402 ,  H01L29/407 ,  H01L29/7397

Abstract: A semiconductor device includes an emitter electrode and a first field plate disposed on one surface of a substrate and spaced apart from each other, a collector electrode disposed on the other surface of the substrate, a trench gate disposed in the substrate, a field diffusion junction disposed in the substrate, and a first contact connecting the trench gate and the first field plate. The first field plate has a first part extending toward the emitter electrode with respect to the first contact and having a first width, and a second part extending toward the field diffusion junction with respect to the first contact and having a second width. The second width is greater than the first width.

Abstract translation: 半导体器件包括发射极和布置在衬底的一个表面上且彼此间隔开的第一场板，设置在衬底的另一个表面上的集电极，设置在衬底中的沟槽栅，场扩散结 设置在所述基板中，以及连接所述沟槽栅极和所述第一场板的第一触点。 第一场板具有相对于第一接触部朝向发射极延伸并且具有第一宽度的第一部分和相对于第一接触部朝向场扩散接合部延伸并具有第二宽度的第二部分。 第二宽度大于第一宽度。

公开(公告)号：US09406543B2

公开(公告)日：2016-08-02

申请号：US14504847

申请日：2014-10-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-Hoon Lee ,  Tae-Geun Kim ,  Chan-Ho Park ,  Hyun-Jung Her

IPC: H01L29/739 ,  H01L21/761 ,  H01L21/265 ,  H01L29/40 ,  H01L29/66 ,  H01L29/06 ,  H01L29/08

CPC classification number: H01L21/761 ,  H01L21/265 ,  H01L21/26513 ,  H01L29/0619 ,  H01L29/0834 ,  H01L29/402 ,  H01L29/4238 ,  H01L29/66348 ,  H01L29/66712 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7802 ,  H01L29/7811 ,  H01L29/7813

Abstract: A semiconductor power device includes a substrate, a plurality of gate electrode structures, a floating well region and a termination ring region. The substrate has a first region and a second region. A plurality of gate electrode structures is formed on the substrate, each of the gate electrode structures extends from the first region to the second region and includes a first gate electrode, a second gate electrode and a connecting portion, the first and second gate electrodes extend in a first direction, and the connecting portion connects end portions of the first and second gate electrodes to each other. The floating well region is doped with impurities between the gate electrode structures in the first region of the substrate, and the floating well region has a first impurity concentration and a first depth. The termination ring region is doped with impurities in the second region of the substrate, is spaced apart from the gate electrode structures, and has a ring shape surrounding the first region, and has the first impurity concentration and the first depth. The semiconductor power device may have a high breakdown voltage.

Abstract translation: 半导体功率器件包括衬底，多个栅电极结构，浮动阱区和端接环区。 衬底具有第一区域和第二区域。 在基板上形成多个栅电极结构，每个栅电极结构从第一区延伸到第二区，并包括第一栅电极，第二栅电极和连接部分，第一和第二栅电极延伸 在第一方向上，连接部将第一和第二栅极的端部彼此连接。 浮置阱区域在衬底的第一区域中的栅电极结构之间掺杂杂质，并且浮置阱区域具有第一杂质浓度和第一深度。 终端环区域在衬底的第二区域中掺杂有杂质，与栅电极结构间隔开，并具有包围第一区域的环状，并且具有第一杂质浓度和第一深度。 半导体功率器件可具有高击穿电压。

公开(公告)号：US09170480B2

公开(公告)日：2015-10-27

申请号：US13918693

申请日：2013-06-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong-gun Lee ,  Seong-Sue Kim ,  Tae-Geun Kim

IPC: G03F1/24 ,  B82Y10/00 ,  B82Y40/00

CPC classification number: G03F1/24 ,  B82Y10/00 ,  B82Y40/00

Abstract: According to example embodiments, a reflective EUV mask may include a mask substrate, a patterned structure and a non-patterned structure on the mask substrate. At least one of the patterned structure and the non-patterned structure may include a thermally treated region configured to reduce a reflectivity of the respective patterned and non-patterned structure.

Abstract translation: 根据示例实施例，反射型EUV掩模可以包括掩模基板，图案化结构和掩模基板上的非图案化结构。 图案化结构和非图案化结构中的至少一个可以包括被配置为减少相应的图案化和非图案化结构的反射率的热处理区域。

公开(公告)号：US20150162443A1

公开(公告)日：2015-06-11

申请号：US14452730

申请日：2014-08-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-Hoon Lee ,  Tae-Geun Kim ,  Chan-Ho Park ,  Hyun-Jung Her

IPC: H01L29/78 ,  H01L27/088

CPC classification number: H01L29/4236 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/1095 ,  H01L29/7397

Abstract: In a semiconductor power device and method of the same, the semiconductor device includes a substrate, a gate electrode structure, first impurity regions, an insulating interlayer, first contact plugs and a first metal pattern. The substrate includes an active region and a termination region. The gate electrode structure includes a first gate electrode and a second gate electrode buried in the substrate, and upper surfaces of the gate electrode structure are lower than an upper surface of the substrate between the first and second gate electrodes. The first impurity regions are formed in the substrate between the first and second electrodes. The insulating interlayer having a flat top surface is formed on the substrate and the gate electrode structure. The first contact plugs are formed through the insulating interlayer, and the first contact plugs contact the first impurity regions. The first metal pattern having a flat top surface is formed on the first contact plugs and the insulating interlayer. Defect of the semiconductor power device may be decreased, and the semiconductor power device may have good electric characteristics.

Abstract translation: 在半导体功率器件及其制造方法中，半导体器件包括衬底，栅电极结构，第一杂质区，绝缘中间层，第一接触插塞和第一金属图案。 衬底包括有源区和端接区。 栅电极结构包括埋在基板中的第一栅极电极和第二栅极电极，栅电极结构的上表面比第一和第二栅电极之间的衬底的上表面低。 在第一和第二电极之间的衬底中形成第一杂质区。 在基板和栅电极结构上形成具有平坦顶面的绝缘中间层。 第一接触插塞通过绝缘中间层形成，并且第一接触插塞接触第一杂质区域。 在第一接触插塞和绝缘中间层上形成具有平坦顶面的第一金属图案。 可以减少半导体功率器件的缺陷，并且半导体功率器件可能具有良好的电特性。