公开(公告)号：US10381344B2

公开(公告)日：2019-08-13

申请号：US15897524

申请日：2018-02-15

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics (Rousset) SAS ,  Commissariat A L'Energie Atomique et aux Energies Alternatives

Inventor： Olivier Weber ,  Emmanuel Richard ,  Philippe Boivin

IPC: H01L27/06 ,  H01L21/84 ,  H01L27/24 ,  H01L21/8249 ,  H01L29/732 ,  H01L45/00 ,  H01L29/417 ,  H01L29/66 ,  H01L27/12 ,  H01L29/08

Abstract: Bipolar transistors and MOS transistors are formed in a common process. A semiconductor layer is arranged on an insulating layer. On a side of the bipolar transistors: an insulating region including the insulating layer is formed; openings are etched through the insulating region to delimit insulating walls; the openings are filled with first epitaxial portions; and the first epitaxial portions and a first region extending under the first epitaxial portions and under the insulating walls are doped. On the side of the bipolar transistors and on a side of the MOS transistors: gate structures are formed; second epitaxial portions are made; and the second epitaxial portions covering the first epitaxial portions are doped.

公开(公告)号：US09653538B2

公开(公告)日：2017-05-16

申请号：US14220542

申请日：2014-03-20

Applicant: STMicroelectronics (Crolles 2) SAS ,  Commissariat A L'Energie Atomique et aux Energies Alternatives

Inventor： Frederic Boeuf ,  Olivier Weber

IPC: H01L21/00 ,  H01L21/762 ,  H01L21/02 ,  H01L29/78 ,  H01L21/84 ,  H01L21/324 ,  H01L29/06 ,  H01L27/12

CPC classification number: H01L29/7847 ,  H01L21/02381 ,  H01L21/02422 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/02667 ,  H01L21/76264 ,  H01L21/76283 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/092 ,  H01L27/12 ,  H01L27/1203 ,  H01L29/0611 ,  H01L29/0642 ,  H01L29/16 ,  H01L29/161 ,  H01L29/7838

Abstract: A substrate of the silicon on insulator type includes a semi-conducting film disposed on a buried insulating layer which is disposed on an unstressed silicon support substrate. The semi-conducting film includes a first film zone of tensile-stressed silicon and a second film zone of tensile-relaxed silicon. Openings through the buried insulating layer permit access to the unstressed silicon support substrate under the first and second film zones. An N channel transistor is formed from the first film zone and a P channel transistor is formed from the second film zone. The second film zone may comprise germanium enriched silicon forming a compressive-stressed region.

公开(公告)号：US12144187B2

公开(公告)日：2024-11-12

申请号：US18335940

申请日：2023-06-15

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Remy Berthelon ,  Olivier Weber

IPC: H10B63/00

Abstract: A method for manufacturing an electronic chip includes providing a semiconductor layer located on an insulator covering a semiconductor substrate. First and second portions of the semiconductor layer are oxidized up to the insulator. Stresses are generated in third portions of the semiconductor layer, and each of the third portions extend between two portions of the semiconductor layer that are oxidized. Cavities are formed which extend at least to the substrate through the second portions and the insulator. Bipolar transistors are formed in at least part of the cavities and first field effect transistors are formed in and on the third portions. Phase change memory points are coupled to the bipolar transistors.

公开(公告)号：US11152430B2

公开(公告)日：2021-10-19

申请号：US16375571

申请日：2019-04-04

Applicant: STMicroelectronics (Rousset) SAS ,  STMicroelectronics (Crolles 2) SAS

Inventor： Philippe Boivin ,  Jean Jacques Fagot ,  Emmanuel Petitprez ,  Emeline Souchier ,  Olivier Weber

IPC: H01L29/73 ,  H01L27/24 ,  H01L45/00

Abstract: The disclosure relates to integrated circuits and methods including one or more rows of transistors. In an embodiment, an integrated circuit includes a row of bipolar transistors including a plurality of first conduction regions, a second conduction region, and a common base between the first conduction regions and the second conduction region. An insulating trench is in contact with each bipolar transistor of the row of bipolar transistors. A conductive layer is on the insulating trench and the common base between the first conduction regions. A spacer layer is between the conductive layer and the first conduction regions.

公开(公告)号：US10332808B2

公开(公告)日：2019-06-25

申请号：US15897003

申请日：2018-02-14

Applicant: Commissariat a l'Energie Atomique et aux Energies Alternatives ,  STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics (Rousset) SAS

Inventor： Franck Julien ,  Stephan Niel ,  Emmanuel Richard ,  Olivier Weber

IPC: H01L21/00 ,  H01L21/84 ,  H01L29/51 ,  H01L21/8234 ,  H01L21/28 ,  H01L27/12 ,  H01L27/092

Abstract: A method of manufacturing first, second, and third transistors of different types inside and on top of first, second, and third semiconductor areas of an integrated circuit, including the steps of: a) depositing a first dielectric layer and a first polysilicon layer on the third areas; b) depositing a second dielectric layer on the second areas; c) depositing an interface layer on the first areas; d) depositing a layer of a material of high permittivity and then a layer of a metallic material on the first and second areas; e) depositing a second polysilicon layer on the first, second, and third areas; f) defining the gates of the transistors in the third areas; and g) defining the gates of the transistors in the first and second areas.

公开(公告)号：US20180175022A1

公开(公告)日：2018-06-21

申请号：US15897524

申请日：2018-02-15

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics (Rousset) SAS ,  Commissariat A L'Energie Atomique et aux Energies Alternatives

Inventor： Olivier Weber ,  Emmanuel Richard ,  Philippe Boivin

IPC: H01L27/06 ,  H01L27/24 ,  H01L21/84 ,  H01L29/732 ,  H01L45/00 ,  H01L21/8249

CPC classification number: H01L27/0623 ,  H01L21/8249 ,  H01L21/84 ,  H01L27/1207 ,  H01L27/2445 ,  H01L29/0813 ,  H01L29/41708 ,  H01L29/66303 ,  H01L29/732 ,  H01L45/06 ,  H01L45/1206 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/16

Abstract: Bipolar transistors and MOS transistors are formed in a common process. A semiconductor layer is arranged on an insulating layer. On a side of the bipolar transistors: an insulating region including the insulating layer is formed; openings are etched through the insulating region to delimit insulating walls; the openings are filled with first epitaxial portions; and the first epitaxial portions and a first region extending under the first epitaxial portions and under the insulating walls are doped. On the side of the bipolar transistors and on a side of the MOS transistors: gate structures are formed; second epitaxial portions are made; and the second epitaxial portions covering the first epitaxial portions are doped.

公开(公告)号：US20240015945A1

公开(公告)日：2024-01-11

申请号：US18347435

申请日：2023-07-05

Applicant: STMicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics International N.V.

Inventor： Olivier Weber ,  Kedar Janardan Dhori ,  Promod Kumar ,  Shafquat Jahan Ahmed ,  Christophe Lecocq ,  Pascal Urard

IPC: H10B10/00 ,  G11C11/417

CPC classification number: H10B10/12 ,  H10B10/18 ,  G11C11/417

Abstract: In one embodiment, a semiconductor device includes a carrier substrate, a buried dielectric region overlying the carrier substrate, and a semiconductor film separated from the carrier substrate by the buried dielectric region. NMOS transistors and PMOS transistors are disposed at a surface of the semiconductor film and coupled together to form a static random access memory (SRAM) cell. The NMOS transistors and the PMOS transistors each include a gate dielectric layer having a thickness greater than three nanometers and an active region in the semiconductor film. The active region of the PMOS transistors are formed from a silicon-germanium alloy.

公开(公告)号：US20230387119A1

公开(公告)日：2023-11-30

申请号：US18324327

申请日：2023-05-26

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Olivier Weber ,  Franck Arnaud

IPC: H01L27/092 ,  H01L27/12 ,  H01L29/06 ,  H01L29/786 ,  H01L21/8238

CPC classification number: H01L27/0922 ,  H01L27/0928 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/78696 ,  H01L21/823807 ,  H01L21/823842 ,  H01L21/823892

Abstract: The semiconductor device of a silicon on insulator type includes a NMOS transistor in a P-type well of the carrier substrate, a PMOS transistor in an N-type well of the carrier substrate, and a power supply circuit configured to generate voltages in the P-type and N-type wells, so as to selectively provide neutral, forward and reverse back bias conditions to the NMOS transistor and the PMOS transistor. The neutral back bias condition is achieved when a first non-zero negative voltage is applied to the P-type well and a first non-zero positive voltage is applied to the N-type well. The NMOS and PMOS transistors are configured to have nominal threshold voltages in the neutral back bias condition.

公开(公告)号：US11818901B2

公开(公告)日：2023-11-14

申请号：US17489425

申请日：2021-09-29

Applicant: STMicroelectronics (Rousset) SAS ,  STMicroelectronics (Crolles 2) SAS

Inventor： Philippe Boivin ,  Jean Jacques Fagot ,  Emmanuel Petitprez ,  Emeline Souchier ,  Olivier Weber

IPC: H01L21/8222 ,  H10B63/00 ,  H10N70/20 ,  H10N70/00

CPC classification number: H10B63/32 ,  H10N70/231 ,  H10N70/826

Abstract: The disclosure relates to integrated circuits and methods including one or more rows of transistors. In an embodiment, an integrated circuit includes a row of bipolar transistors including a plurality of first conduction regions, a second conduction region, and a common base between the first conduction regions and the second conduction region. An insulating trench is in contact with each bipolar transistor of the row of bipolar transistors. A conductive layer is on the insulating trench and the common base between the first conduction regions. A spacer layer is between the conductive layer and the first conduction regions.

公开(公告)号：US11653582B2

公开(公告)日：2023-05-16

申请号：US16184246

申请日：2018-11-08

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics (Rousset) SAS

Inventor： Franck Arnaud ,  David Galpin ,  Stephane Zoll ,  Olivier Hinsinger ,  Laurent Favennec ,  Jean-Pierre Oddou ,  Lucile Broussous ,  Philippe Boivin ,  Olivier Weber ,  Philippe Brun ,  Pierre Morin

IPC: H01L45/00 ,  H01L27/24 ,  G11C13/00

CPC classification number: H10N70/8616 ,  G11C13/0004 ,  G11C13/0069 ,  H10B63/30 ,  H10B63/80 ,  H10N70/011 ,  H10N70/021 ,  H10N70/231 ,  H10N70/826 ,  H10N70/8265 ,  H10N70/8413 ,  H10N70/882 ,  G11C2013/008

Abstract: An electronic chip includes memory cells made of a phase-change material and a transistor. First and second vias extend from the transistor through an intermediate insulating layer to a same height. A first metal level including a first interconnection track in contact with the first via is located over the intermediate insulating layer. A heating element for heating the phase-change material is located on the second via, and the phase-change material is located on the heating element. A second metal level including a second interconnection track is located above the phase-change material. A third via extends from the phase-change material to the second interconnection track.