知搜-全球专利检索

  1. 登录
  2. 注册

搜索结果

23 条记录 (耗时 0.015 秒)

    Three-dimensional semiconductor memory device
    3.
    发明授权
    Three-dimensional semiconductor memory device 有权

    公开(公告)号：US11315914B2

    公开(公告)日：2022-04-26

    申请号：US16890653

    申请日：2020-06-02

    申请人： SK hynix Inc.

    发明人： Sang Hyun Sung ,  Young Ki Kim ,  Jin Ho Kim ,  Byung Hyun Jun

    IPC分类号： H01L27/11582 ,  H01L25/18 ,  H01L23/00 ,  H01L27/11573 ,  H01L23/528

    摘要： A semiconductor memory device includes: a first pad layer in a surface of a memory chip including a cell region in which a memory cell array coupled to a plurality of row lines and a step region including staggered step portions of the plurality of row lines, and including a plurality of first pads that are coupled to the step portions; a second pad layer in a surface of a circuit chip bonded to the surface of the memory chip, and having a plurality of second pads coupled to a plurality of pass transistors defined in the circuit chip; a first redistribution line disposed in the first pad layer that couples one of the step portions and one of the pass transistors; and a second redistribution line disposed in the second pad layer that couples another one of the step portions and another one of the pass transistors.

    Memory device having vertical structure
    4.
    发明授权
    Memory device having vertical structure 有权

    公开(公告)号：US12101930B2

    公开(公告)日：2024-09-24

    申请号：US17828417

    申请日：2022-05-31

    申请人： SK hynix Inc.

    发明人： Jin Ho Kim ,  Kwang Hwi Park ,  Sang Hyun Sung ,  Sung Lae Oh ,  Chang Woon Choi

    IPC分类号： H10B41/27 ,  H10B41/40 ,  H10B43/27 ,  H10B43/40

    CPC分类号： H10B41/27 ,  H10B41/40 ,  H10B43/27 ,  H10B43/40

    摘要： A memory device includes a cell wafer including a memory cell array; and a peripheral wafer including a row control circuit, a column control circuit and a peripheral circuit which control the memory cell array, and stacked on and bonded to the cell wafer in a first direction. The peripheral wafer includes a first substrate having a first surface and a second surface which face away from each other in the first direction; a first logic structure disposed on the first surface of the first substrate, and including the row control circuit and the column control circuit; and a second logic structure disposed on the second surface of the first substrate, and including the peripheral circuit.

    Semiconductor memory device
    5.
    发明授权
    Semiconductor memory device 有权

    公开(公告)号：US11387216B2

    公开(公告)日：2022-07-12

    申请号：US16907094

    申请日：2020-06-19

    申请人： SK hynix Inc.

    发明人： Jin Ho Kim ,  Young Ki Kim ,  Sang Hyun Sung ,  Sung Lae Oh ,  Byung Hyun Jun

    IPC分类号： H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L23/552 ,  H01L49/02

    摘要： A semiconductor memory device includes a plurality of first pads disposed in one surface of a memory chip which includes a memory cell array and a plurality of row lines coupled to the memory cell array, and coupled to the row lines, respectively; and a plurality of second pads disposed in one surface of a circuit chip which is boned to the one surface of the memory chip, coupled to pass transistors, respectively, of the circuit chip, and bonded to the first pads, respectively. The second pads are aligned with the pass transistors, with the same pitch as a pitch of the pass transistors.

    Memory device having vertical structure
    6.
    发明授权
    Memory device having vertical structure 有权

    公开(公告)号：US11380702B2

    公开(公告)日：2022-07-05

    申请号：US17145209

    申请日：2021-01-08

    申请人： SK hynix Inc.

    发明人： Jin Ho Kim ,  Kwang Hwi Park ,  Sang Hyun Sung ,  Sung Lae Oh ,  Chang Woon Choi

    IPC分类号： H01L27/11556 ,  H01L27/11573 ,  H01L27/11582 ,  H01L27/11526

    摘要： A memory device includes a cell wafer including a memory cell array; and a peripheral wafer including a row control circuit, a column control circuit and a peripheral circuit which control the memory cell array, and stacked on and bonded to the cell wafer in a first direction. The peripheral wafer includes a first substrate having a first surface and a second surface which face away from each other in the first direction; a first logic structure disposed on the first surface of the first substrate, and including the row control circuit and the column control circuit; and a second logic structure disposed on the second surface of the first substrate, and including the peripheral circuit.

    Semiconductor device
    7.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US11373701B2

    公开(公告)日：2022-06-28

    申请号：US17171632

    申请日：2021-02-09

    申请人： SK hynix Inc.

    发明人： Sang Hyun Sung ,  Sung Lae Oh ,  Je Hyun Choi

    IPC分类号： G11C5/06 ,  G11C11/417 ,  G11C11/412 ,  H01L27/11 ,  H01L23/00

    摘要： A semiconductor device includes a first wafer including a row decoder region in which a plurality of pass transistors are arranged in a row direction and a column direction; a plurality of first bonding pads, respectively coupled to the plurality of pass transistors that are disposed in a plurality of rows on one surface of the first wafer in the row decoder region; and a plurality of second bonding pads disposed on the one surface of the first wafer in the row decoder region, wherein the plurality of second bonding pads are disposed in a different row from the plurality of first bonding pads and are offset in the row direction with respect to the plurality of first bonding pads.

    Semiconductor memory device including unit page buffer blocks having four page buffer pairs
    8.
    发明授权
    Semiconductor memory device including unit page buffer blocks having four page buffer pairs 有权

    公开(公告)号：US11960408B2

    公开(公告)日：2024-04-16

    申请号：US18053003

    申请日：2022-11-07

    申请人： SK hynix Inc.

    发明人： Dong Hyuk Kim ,  Tae Sung Park ,  Sang Hyun Sung ,  Sung Lae Oh ,  Soo Nam Jung

    IPC分类号： G06F12/00 ,  G06F12/0882 ,  G06F12/0895 ,  G06F12/123

    CPC分类号： G06F12/0895 ,  G06F12/0882 ,  G06F12/125

    摘要： A unit page buffer block includes first to fourth page buffer pairs. Each of the page buffer pairs includes a common column decoder block; and an upper page buffer stage and a lower page buffer stage electrically and commonly connected to the common column decoder block. Each of the upper page buffer stages includes an upper selection block; an upper latch block; and an upper cache block. Each of the lower page buffer stage includes a lower selection block; a lower latch block; and a lower cache block. Each of the upper selection blocks includes first to fourth sub-selection blocks. Each of the upper and lower latch blocks includes first to twelfth upper sub-latch blocks. Each of the upper and lower cache blocks includes first to twelfth upper sub-cache blocks. Each of the common column decoder block includes first to third sub-common column decoder blocks arranged in a row direction.

    Memory device including row decoder
    9.
    发明授权
    Memory device including row decoder 有权

    公开(公告)号：US11770933B2

    公开(公告)日：2023-09-26

    申请号：US17165097

    申请日：2021-02-02

    申请人： SK hynix Inc.

    发明人： Jin Ho Kim ,  Young Ki Kim ,  Sang Hyun Sung ,  Sung Lae Oh ,  Byung Hyun Jeon

    IPC分类号： H10B43/40 ,  H01L23/522 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27

    CPC分类号： H10B43/40 ,  H01L23/5226 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27

    摘要： A memory device includes a substrate defined with a first cell region and a second cell region, and a row decoder region between the first and second cell regions; a peripheral circuit defined in the first and second cell regions of the substrate; pass transistors defined in the row decoder region of the substrate; bottom wiring layers disposed in a first dielectric layer covering the peripheral circuit and the pass transistors; a memory cell array defined on the first dielectric layer; a second dielectric layer defined on the first dielectric layer, and covering the memory cell array; top wiring layers disposed in a third dielectric layer defined on the second dielectric layer; and global lines disposed in the row decoder region, and configured to transfer operating voltages to the pass transistors, wherein the global lines are disposed only in at least one bottom wiring layer from among the bottom and top wiring layers.

    Three-dimensional memory device and manufacturing method thereof
    10.
    发明授权
    Three-dimensional memory device and manufacturing method thereof 有权

    公开(公告)号：US11569265B2

    公开(公告)日：2023-01-31

    申请号：US17145229

    申请日：2021-01-08

    申请人： SK hynix Inc.

    发明人： Sung Lae Oh ,  Jin Ho Kim ,  Sang Woo Park ,  Sang Hyun Sung

    IPC分类号： H01L27/11582 ,  H01L23/522 ,  H01L21/768 ,  H01L27/11556 ,  H01L23/528

    摘要： A three-dimensional memory device includes an electrode structure including a plurality of electrode layers and a plurality of interlayer dielectric layers which are alternately stacked on a substrate; a first stairway structure and a second stairway structure defined in the electrode structure, and positioned at different heights from each other; a sidewall of the electrode structure formed due to a difference in height between the first stairway structure and the second stairway structure; and a dielectric support passing through the electrode structure, and isolating a corner portion of the sidewall from the plurality of electrode layers.