公开(公告)号：US12101930B2

公开(公告)日：2024-09-24

申请号：US17828417

申请日：2022-05-31

Applicant: SK hynix Inc.

Inventor： Jin Ho Kim ,  Kwang Hwi Park ,  Sang Hyun Sung ,  Sung Lae Oh ,  Chang Woon Choi

IPC: H10B41/27 ,  H10B41/40 ,  H10B43/27 ,  H10B43/40

CPC classification number: H10B41/27 ,  H10B41/40 ,  H10B43/27 ,  H10B43/40

Abstract: A memory device includes a cell wafer including a memory cell array; and a peripheral wafer including a row control circuit, a column control circuit and a peripheral circuit which control the memory cell array, and stacked on and bonded to the cell wafer in a first direction. The peripheral wafer includes a first substrate having a first surface and a second surface which face away from each other in the first direction; a first logic structure disposed on the first surface of the first substrate, and including the row control circuit and the column control circuit; and a second logic structure disposed on the second surface of the first substrate, and including the peripheral circuit.

公开(公告)号：US11705397B2

公开(公告)日：2023-07-18

申请号：US17225517

申请日：2021-04-08

Applicant: SK hynix Inc.

Inventor： Chan Ho Yoon ,  Jin Ho Kim

IPC: H01L23/528 ,  H01L23/522 ,  H01L21/768 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27 ,  H10B43/40

CPC classification number: H01L23/5283 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/5226 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27 ,  H10B43/40

Abstract: A three-dimensional memory device includes a plurality of row lines stacked alternately with a plurality of interlayer dielectric layers in a vertical direction on a substrate, and each of the plurality of row lines having a projection from a side surface thereof; and a plurality of vias extending in the vertical direction from the substrate, each coupled to the projection of a corresponding row line, and electrically coupling the plurality of row lines to a peripheral circuit defined below the substrate.

公开(公告)号：US11387216B2

公开(公告)日：2022-07-12

申请号：US16907094

申请日：2020-06-19

Applicant: SK hynix Inc.

Inventor： Jin Ho Kim ,  Young Ki Kim ,  Sang Hyun Sung ,  Sung Lae Oh ,  Byung Hyun Jun

IPC: H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L23/552 ,  H01L49/02

Abstract: A semiconductor memory device includes a plurality of first pads disposed in one surface of a memory chip which includes a memory cell array and a plurality of row lines coupled to the memory cell array, and coupled to the row lines, respectively; and a plurality of second pads disposed in one surface of a circuit chip which is boned to the one surface of the memory chip, coupled to pass transistors, respectively, of the circuit chip, and bonded to the first pads, respectively. The second pads are aligned with the pass transistors, with the same pitch as a pitch of the pass transistors.

公开(公告)号：US11380702B2

公开(公告)日：2022-07-05

申请号：US17145209

申请日：2021-01-08

Applicant: SK hynix Inc.

Inventor： Jin Ho Kim ,  Kwang Hwi Park ,  Sang Hyun Sung ,  Sung Lae Oh ,  Chang Woon Choi

IPC: H01L27/11556 ,  H01L27/11573 ,  H01L27/11582 ,  H01L27/11526

Abstract: A memory device includes a cell wafer including a memory cell array; and a peripheral wafer including a row control circuit, a column control circuit and a peripheral circuit which control the memory cell array, and stacked on and bonded to the cell wafer in a first direction. The peripheral wafer includes a first substrate having a first surface and a second surface which face away from each other in the first direction; a first logic structure disposed on the first surface of the first substrate, and including the row control circuit and the column control circuit; and a second logic structure disposed on the second surface of the first substrate, and including the peripheral circuit.

公开(公告)号：US11955429B2

公开(公告)日：2024-04-09

申请号：US18328416

申请日：2023-06-02

Applicant: SK hynix Inc.

Inventor： Chan Ho Yoon ,  Jin Ho Kim

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27 ,  H10B43/40

CPC classification number: H01L23/5283 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/5226 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27 ,  H10B43/40

Abstract: A method for manufacturing a three-dimensional memory device, comprises: forming, on a substrate, a sacrificial layer including a plurality of sacrificial patterns for vias and a sacrificial pattern for a row line; forming an interlayer dielectric layer that covers the sacrificial pattern for a row line and the sacrificial pattern for a via coupled to the sacrificial pattern for a row line and that has a plurality of holes exposing sacrificial patterns for vias, from among the plurality of sacrificial patterns for vias, that are not coupled to the sacrificial pattern for a row line; forming a plurality of first conductive patterns in the plurality of holes; repeating the forming of the sacrificial layer; and replacing the plurality of sacrificial layers with a conductive material.

公开(公告)号：US20230410909A1

公开(公告)日：2023-12-21

申请号：US18459357

申请日：2023-08-31

Applicant: SK hynix Inc.

Inventor： Jin Ho Kim ,  Young Ki KIM ,  Sang Hyun SUNG ,  Sung Lae OH ,  Byung Hyun JEON

IPC: G11C16/08 ,  G11C5/06 ,  G11C16/04 ,  H10B41/10 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40

CPC classification number: G11C16/08 ,  G11C5/063 ,  G11C16/0483 ,  H10B41/10 ,  H10B43/40 ,  H10B41/40 ,  H10B43/10 ,  H10B43/35 ,  H10B41/35

Abstract: A memory device includes a first semiconductor structure including pass transistors defined in a row decoder region of a substrate, a first bonding layer including first bonding pads, and bottom wiring layers disposed between the substrate and the first bonding layer; a second semiconductor structure including a second bonding layer including second bonding pads bonded to the first bonding pads, a memory cell array, and a top wiring layer disposed between the second bonding layer and the memory cell array; and global lines disposed in the row decoder region, and configured to transfer operating voltages to the pass transistors, wherein the bottom wiring layers include bottom wiring layers of a first tier and bottom wiring layers of a second tier disposed over the bottom wiring layers of the first tier, and the global lines are disposed in at least one of the bottom wiring layers of the first tier.

公开(公告)号：US11770933B2

公开(公告)日：2023-09-26

申请号：US17165097

申请日：2021-02-02

Applicant: SK hynix Inc.

Inventor： Jin Ho Kim ,  Young Ki Kim ,  Sang Hyun Sung ,  Sung Lae Oh ,  Byung Hyun Jeon

IPC: H10B43/40 ,  H01L23/522 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27

CPC classification number: H10B43/40 ,  H01L23/5226 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27

Abstract: A memory device includes a substrate defined with a first cell region and a second cell region, and a row decoder region between the first and second cell regions; a peripheral circuit defined in the first and second cell regions of the substrate; pass transistors defined in the row decoder region of the substrate; bottom wiring layers disposed in a first dielectric layer covering the peripheral circuit and the pass transistors; a memory cell array defined on the first dielectric layer; a second dielectric layer defined on the first dielectric layer, and covering the memory cell array; top wiring layers disposed in a third dielectric layer defined on the second dielectric layer; and global lines disposed in the row decoder region, and configured to transfer operating voltages to the pass transistors, wherein the global lines are disposed only in at least one bottom wiring layer from among the bottom and top wiring layers.

公开(公告)号：US11715711B2

公开(公告)日：2023-08-01

申请号：US17151464

申请日：2021-01-18

Applicant: SK hynix Inc.

Inventor： Tae Sung Park ,  Jin Ho Kim

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H10B41/27 ,  H10B43/27

CPC classification number: H01L24/08 ,  H01L25/0657 ,  H01L25/18 ,  H10B41/27 ,  H10B43/27 ,  H01L2224/08145 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: A memory device includes an active region with a drain; a plurality of memory blocks arranged in a first direction; and a plurality of pass transistors formed in the active region and sharing the drain, each one of the plurality of pass transistors configured to transfer an operating voltage from the drain to a corresponding one of the plurality of memory blocks in response to a block select signal. The plurality of pass transistors is divided into first pass transistors and second pass transistors. A channel length direction of the first pass transistors and a channel length direction of the second pass transistors are different from each other.

公开(公告)号：US11569265B2

公开(公告)日：2023-01-31

申请号：US17145229

申请日：2021-01-08

Applicant: SK hynix Inc.

Inventor： Sung Lae Oh ,  Jin Ho Kim ,  Sang Woo Park ,  Sang Hyun Sung

IPC: H01L27/11582 ,  H01L23/522 ,  H01L21/768 ,  H01L27/11556 ,  H01L23/528

Abstract: A three-dimensional memory device includes an electrode structure including a plurality of electrode layers and a plurality of interlayer dielectric layers which are alternately stacked on a substrate; a first stairway structure and a second stairway structure defined in the electrode structure, and positioned at different heights from each other; a sidewall of the electrode structure formed due to a difference in height between the first stairway structure and the second stairway structure; and a dielectric support passing through the electrode structure, and isolating a corner portion of the sidewall from the plurality of electrode layers.

公开(公告)号：US11527544B2

公开(公告)日：2022-12-13

申请号：US17014370

申请日：2020-09-08

Applicant: SK hynix Inc.

Inventor： Sang Hyun Sung ,  Jin Ho Kim ,  Sung Lae Oh

IPC: H01L27/11539 ,  H01L23/528 ,  H01L27/11556 ,  H01L27/11582

Abstract: A three-dimensional memory device includes an electrode structure including a plurality of interlayer dielectric layers and a plurality of electrode layers which are alternately stacked on a first substrate, each of the plurality of electrode layers having a pad part which does not overlap with another electrode layer positioned on the electrode layer; a pass transistor positioned below the first substrate; and a first contact passing through the electrode structure from the pad part of one of the plurality of electrode layers, and coupling the pad part and the pass transistor.