A method for manufacturing a three-dimensional memory device, comprises: forming, on a substrate, a sacrificial layer including a plurality of sacrificial patterns for vias and a sacrificial pattern for a row line; forming an interlayer dielectric layer that covers the sacrificial pattern for a row line and the sacrificial pattern for a via coupled to the sacrificial pattern for a row line and that has a plurality of holes exposing sacrificial patterns for vias, from among the plurality of sacrificial patterns for vias, that are not coupled to the sacrificial pattern for a row line; forming a plurality of first conductive patterns in the plurality of holes; repeating the forming of the sacrificial layer; and replacing the plurality of sacrificial layers with a conductive material.