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    Semiconductor memory device with chip-to-chip bonding structure
    1.
    发明授权
    Semiconductor memory device with chip-to-chip bonding structure 有权

    公开(公告)号：US11374016B2

    公开(公告)日：2022-06-28

    申请号：US16811481

    申请日：2020-03-06

    申请人： SK hynix Inc.

    发明人： Sung Lae Oh ,  Dong Hyuk Kim ,  Tae Sung Park

    IPC分类号： H01L27/1157 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11573 ,  G06F3/06 ,  G11C5/06 ,  G11C11/4094 ,  G11C5/02 ,  G11C11/4097 ,  G11C11/4074 ,  G11C11/4093

    摘要： A semiconductor memory device includes: a plurality of page buffers disposed on a substrate; and a plurality of pads exposed to one surface of a dielectric layer covering the page buffers, and coupled to the respective page buffers. The substrate comprises a plurality of high voltage regions and a plurality of low voltage regions which are alternately disposed in a second direction crossing a first direction. Each of the plurality of page buffers comprises a sensing unit and a bit line select transistor coupled between the sensing unit and the one of the plurality of pads. The bit line select transistors of the plurality of page buffers are disposed in the plurality of high voltage regions, and the plurality of pads are distributed and disposed in a plurality of pad regions which correspond to the high voltage regions and are spaced apart from each other in the second direction.

    Semiconductor device including page buffer
    2.
    发明授权
    Semiconductor device including page buffer 有权

    公开(公告)号：US11232840B2

    公开(公告)日：2022-01-25

    申请号：US16932522

    申请日：2020-07-17

    申请人： SK hynix Inc.

    发明人： Sung Lae Oh ,  Dong Hyuk Kim ,  Tae Sung Park ,  Soo Nam Jung

    IPC分类号： G11C16/24

    摘要： A semiconductor device including a page buffer is disclosed, which reduces the number of lines of the page buffer. The semiconductor device includes a plurality of bit lines, classified into a first group and a second group, that are arranged alternating, a first page buffer circuit coupled to the plurality of bit lines and a plurality of connection lines corresponding to the plurality of bit lines, and a second page buffer circuit coupled to the plurality of connection lines. Each of the first group and the second group includes a plurality of bit-line pairs classified into odd bit lines and even bit lines. The plurality of connection lines includes odd connection lines and even connection lines, and odd connection lines corresponding to the odd bit lines are arranged contiguous to each other, and even connection lines corresponding to the even bit lines are arranged contiguous to each other.

    Semiconductor memory device including page buffers
    3.
    发明授权
    Semiconductor memory device including page buffers 有权

    公开(公告)号：US11114152B1

    公开(公告)日：2021-09-07

    申请号：US17010126

    申请日：2020-09-02

    申请人： SK hynix Inc.

    发明人： Dong Hyuk Kim ,  Sung Lae Oh ,  Yeong Taek Lee ,  Tae Sung Park ,  Soo Nam Jung

    IPC分类号： G11C11/40 ,  G11C5/06 ,  G11C11/4093 ,  G11C11/4091 ,  G11C11/4094

    摘要： A semiconductor memory device includes a memory cell; and a page buffer including a sensing circuit that is coupled to the memory cell through a bit line. The page buffer includes a first transistor included in the sensing circuit; and a second transistor not included in the sensing circuit. A cross-sectional dimension of a first contact which is coupled to the first transistor and a cross-sectional dimension of a second contact which is coupled to the second transistor are different from each other. The cross-sectional dimension of the second contact is smaller than the cross-sectional dimension of the first contact.

    SEMICONDUCTOR MEMORY DEVICE WITH PAGE BUFFERS
    4.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE WITH PAGE BUFFERS 有权

    公开(公告)号：US20210057019A1

    公开(公告)日：2021-02-25

    申请号：US16784837

    申请日：2020-02-07

    申请人： SK hynix Inc.

    发明人： Sung Lae Oh ,  Dong Hyuk Kim ,  Tae Sung Park ,  Soo Nam Jung

    IPC分类号： G11C11/4094 ,  G11C7/10 ,  G11C29/00 ,  G11C11/4093 ,  G11C29/02 ,  G11C29/44 ,  G11C5/02

    摘要： Disclosed is a semiconductor memory device. The semiconductor memory device may include: a memory cell array; and a cache latch circuit configured to exchange data with the memory cell array through a plurality of bit lines extended in a second direction crossing a first direction, and comprising a plurality of cache latches arranged in a plurality of column in the first direction and in a plurality of rows in the second direction. Each of the cache latches may be coupled to any one of a plurality of input/output (IO) pins. Cache latches coupled to the IO pins at the same time may constitute one IO cache latch unit. The cache latches included in the one IO cache latch unit may be arranged in 2×2 array units.

    Semiconductor memory device including unit page buffer blocks having four page buffer pairs
    5.
    发明授权
    Semiconductor memory device including unit page buffer blocks having four page buffer pairs 有权

    公开(公告)号：US11960408B2

    公开(公告)日：2024-04-16

    申请号：US18053003

    申请日：2022-11-07

    申请人： SK hynix Inc.

    发明人： Dong Hyuk Kim ,  Tae Sung Park ,  Sang Hyun Sung ,  Sung Lae Oh ,  Soo Nam Jung

    IPC分类号： G06F12/00 ,  G06F12/0882 ,  G06F12/0895 ,  G06F12/123

    CPC分类号： G06F12/0895 ,  G06F12/0882 ,  G06F12/125

    摘要： A unit page buffer block includes first to fourth page buffer pairs. Each of the page buffer pairs includes a common column decoder block; and an upper page buffer stage and a lower page buffer stage electrically and commonly connected to the common column decoder block. Each of the upper page buffer stages includes an upper selection block; an upper latch block; and an upper cache block. Each of the lower page buffer stage includes a lower selection block; a lower latch block; and a lower cache block. Each of the upper selection blocks includes first to fourth sub-selection blocks. Each of the upper and lower latch blocks includes first to twelfth upper sub-latch blocks. Each of the upper and lower cache blocks includes first to twelfth upper sub-cache blocks. Each of the common column decoder block includes first to third sub-common column decoder blocks arranged in a row direction.

    Semiconductor memory device with cache latches
    6.
    发明授权
    Semiconductor memory device with cache latches 有权

    公开(公告)号：US11107521B2

    公开(公告)日：2021-08-31

    申请号：US16784837

    申请日：2020-02-07

    申请人： SK hynix Inc.

    发明人： Sung Lae Oh ,  Dong Hyuk Kim ,  Tae Sung Park ,  Soo Nam Jung

    IPC分类号： G11C7/10 ,  G11C11/4094 ,  G11C29/00 ,  G11C5/02 ,  G11C29/02 ,  G11C29/44 ,  G11C11/4093

    摘要： A semiconductor memory device may include a memory cell array; and a cache latch circuit that exchanges data with the memory cell array through a plurality of bit lines extended in a second direction crossing a first direction. The memory cell array may include a plurality of cache latches arranged in a plurality of columns in the first direction and in a plurality of rows in the second direction. Each of the cache latches may be coupled to any one of a plurality of input/output (IO) pins. Cache latches coupled to the IO pins at the same time may constitute one IO cache latch unit. The cache latches included in the one IO cache latch unit may be arranged in 2×2 array units.

    Semiconductor memory device and manufacturing method thereof
    8.
    发明授权
    Semiconductor memory device and manufacturing method thereof 有权

    公开(公告)号：US10896918B1

    公开(公告)日：2021-01-19

    申请号：US16723460

    申请日：2019-12-20

    申请人： SK hynix Inc.

    发明人： Sung Lae Oh ,  Dong Hyuk Kim ,  Tae Sung Park ,  Soo Nam Jung

    IPC分类号： H01L27/11582 ,  H01L23/528 ,  H01L23/522 ,  H01L27/11526 ,  H01L25/00 ,  H01L25/18 ,  H01L23/00 ,  H01L27/11573 ,  H01L27/11556 ,  H01L21/768 ,  H01L21/311

    摘要： A semiconductor memory device includes a stack disposed over a substrate defined with cell and connection areas; channel structures passing through the stack in the cell area; and slits defined in the stack. The stack includes first dielectric layers separately staked in the cell and connection areas; electrode layers disposed alternately with the first dielectric layers in the cell area and a periphery of the connection area adjacent to the slits; and second dielectric layers disposed alternately with the first dielectric layers in a central part of the connection area distant from the slits. A distance between the slits in the connection area is larger than a distance between the slits in the cell area, and, at a boundary between the periphery and the central part of the connection area, the electrode layers and the second dielectric layers disposed at the same layers are in contact with each other.