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公开(公告)号:US11469252B2
公开(公告)日:2022-10-11
申请号:US16942093
申请日:2020-07-29
Applicant: Samsung Electronics Co., Ltd.
Inventor: Seok Han Park , Yong Seok Kim , Hui-Jung Kim , Satoru Yamada , Kyung Hwan Lee , Jae Ho Hong , Yoo Sang Hwang
IPC: H01L27/11597 , H01L27/1159 , H01L29/06 , H01L29/45 , H01L29/78 , H01L29/786 , H01L49/02
Abstract: A semiconductor device is provided. The semiconductor device includes a first stacked structure including a plurality of first insulating patterns and a plurality of first semiconductor patterns alternately stacked on a substrate, the first stacked structure extending in a first direction parallel to an upper surface of the substrate, a first conductive pattern on one side surface of the first stacked structure, the first conductive pattern extending in a second direction crossing the upper surface of the substrate, and a first ferroelectric layer between the first stacked structure and the first conductive pattern, the first ferroelectric layer extending in the second direction, wherein each of the first semiconductor patterns includes a first impurity region, a first channel region and a second impurity region which are sequentially arranged along the first direction.
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公开(公告)号:US10998301B2
公开(公告)日:2021-05-04
申请号:US16531778
申请日:2019-08-05
Applicant: Samsung Electronics Co., Ltd.
Inventor: Kohji Kanamori , Hyun Mog Park , Yong Seok Kim , Kyung Hwan Lee , Jun Hee Lim , Jee Hoon Han
IPC: H01L25/18 , H01L23/00 , H01L27/11556 , H01L27/11582
Abstract: A semiconductor device includes a first semiconductor structure including circuit devices and first bonding pads; and a second semiconductor structure connected to the first semiconductor structure, the second semiconductor structure including a base layer; a first memory cell structure including first gate electrodes and first channels penetrating through the first gate electrodes; a second memory cell structure including second gate electrodes and second channels penetrating through the second gate electrodes; bit lines between the first and the second memory cell structures, and electrically connected to the first and second channels in common; first and second conductive layers on the second surface of the base layer; a pad insulating layer having an opening exposing a portion of the second conductive layer; and second bonding pads disposed to correspond to the first bonding pads in a lower portion of the second memory cell structure.
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公开(公告)号:US20240040795A1
公开(公告)日:2024-02-01
申请号:US18351407
申请日:2023-07-12
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Bong Yong LEE , Yong Seok Kim
IPC: H10B51/20 , H10B51/10 , H01L29/66 , H01L29/78 , H01L23/528
CPC classification number: H10B51/20 , H10B51/10 , H01L29/6684 , H01L29/78391 , H01L23/5283
Abstract: A semiconductor device comprises a substrate that extends in first and second directions and includes a cell region and an extension region that extends from the cell region in the first direction, first and second insulating layers alternately stacked on the substrate in a third direction, a conductive line disposed on one sidewall of the second insulating layer in the second direction, a conductive pillar that extends in the third direction and penetrates through the first insulating layer, a semiconductor layer disposed on one sidewall of the conductive pillar and that extends in the third direction, and a ferroelectric layer disposed between the conductive line and the semiconductor layer and that extends in the third direction. The conductive line includes first and second conductive patterns spaced apart from each other in the second direction, and the second insulating layer is disposed between the first and second conductive patterns.
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公开(公告)号:US11729976B2
公开(公告)日:2023-08-15
申请号:US17370628
申请日:2021-07-08
Applicant: Samsung Electronics Co., Ltd.
Inventor: Kohji Kanamori , Yong Seok Kim , Kyung Hwan Lee , Jun Hee Lim , Jee Hoon Han
IPC: H10B43/27 , H01L23/528 , H01L25/18 , H01L25/00 , G11C16/08 , H01L29/78 , H01L29/10 , G11C16/04 , H10B43/40
CPC classification number: H10B43/27 , G11C16/0483 , G11C16/08 , H01L23/528 , H01L25/18 , H01L25/50 , H01L29/1037 , H01L29/7827 , H10B43/40
Abstract: A semiconductor device includes a lower stack structure that includes a lower word line, an upper stack structure that is on the lower stack structure and includes an upper word line, a decoder that is adjacent to the lower stack structure and the upper stack structure, a signal interconnection that is connected to the decoder, a lower selector that is connected to the signal interconnection and further connected to the lower word line, and an upper selector that is connected to the signal interconnection, isolated from direct contact with the lower selector, and further connected to the upper word line.
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公开(公告)号:US11723290B2
公开(公告)日:2023-08-08
申请号:US17514086
申请日:2021-10-29
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Kyung Hwan Lee , Yong Seok Kim , Tae Hun Kim , Seok Han Park , Satoru Yamada , Jae Ho Hong
CPC classification number: H10N70/24 , H10B63/34 , H10N70/023 , H10N70/231 , H10N70/826 , H10N70/8833
Abstract: A semiconductor device includes a stack structure on a substrate, the stack structure including alternating gate electrodes and insulating layers stacked along a first direction, a vertical opening through the stack structure along the first direction, the vertical opening including a channel structure having a semiconductor layer on an inner sidewall of the vertical opening, and a variable resistive material on the semiconductor layer, a vacancy concentration in the variable resistive material varies along its width to have a higher concentration closer to a center of the channel structure than to the semiconductor layer, and an impurity region on the substrate, the semiconductor layer contacting the impurity region at a bottom of the channel structure.
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公开(公告)号:US11711918B2
公开(公告)日:2023-07-25
申请号:US17227793
申请日:2021-04-12
Applicant: Samsung Electronics Co., Ltd.
Inventor: Kyung Hwan Lee , Yong Seok Kim , Hyun Cheol Kim , Satoru Yamada , Sung Won Yoo , Jae Ho Hong
Abstract: Provided is a semiconductor memory device. The semiconductor memory device comprises a first semiconductor pattern including a first impurity region, a second impurity region, and a channel region, the first impurity region spaced apart from a substrate in a first direction and having a first conductivity type, the second impurity region having a second conductivity type different from the first conductivity type, and the channel region between the first impurity region and the second impurity region, a first conductive connection line connected to the first impurity region and extending in a second direction different from the first direction and a first gate structure extending in the first direction and including a first gate electrode and a first gate insulating film, wherein the first gate electrode penetrates the channel region and the first gate insulating film is between the first gate electrode and the semiconductor pattern.
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公开(公告)号:US20230147083A1
公开(公告)日:2023-05-11
申请号:US17846158
申请日:2022-06-22
Applicant: Samsung Electronics Co., Ltd.
Inventor: Min Hee Cho , Dong Il Bae , Won Sok Lee , Yong Seok Kim
IPC: H01L27/11573 , H01L27/11519 , H01L27/11556 , H01L27/11565 , H01L27/11582 , H01L27/11526
CPC classification number: H01L27/11573 , H01L27/11519 , H01L27/11556 , H01L27/11565 , H01L27/11582 , H01L27/11526
Abstract: A semiconductor memory device includes a cell area and a peripheral area, a base insulating layer including opposed first front and rear surfaces in the cell area, a first semiconductor substrate including opposed second front and rear surfaces in the peripheral area, an active pattern on the first front surface, a first conductive line extending in a first direction on a side of the active pattern, a capacitor structure on the active pattern, a first circuit element on the second front surface, and a second conductive line extending in a second direction intersecting the first direction on the first rear surface and the second rear surface. The active pattern extends in a vertical direction intersecting the first direction and the second direction to electrically connect the second conductive line to the capacitor structure.
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公开(公告)号:US10831362B2
公开(公告)日:2020-11-10
申请号:US16104704
申请日:2018-08-17
Applicant: Samsung Electronics Co., Ltd.
Inventor: Nam Jo Heo , Sang Yup Lee , Yong Seok Kim , Kwang Sub Son
IPC: G06F3/0488 , G06F3/0481 , G06F3/0484
Abstract: A mobile terminal and a method of supporting an object change for the same are provided. The mobile terminal includes a display unit for outputting at least one object, and a control unit for controlling at least one of directly displaying, in response to a signal for changing the output object into a second object having a similar function but being of a different type than the output object, the second object on the display unit without a screen transition, and for outputting, in response to a signal for changing the output object into a second object having a similar function but being of a different type than the output object, a guide frame on the display unit so as to facilitate change of the output object without a screen transition.
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公开(公告)号:US10319427B2
公开(公告)日:2019-06-11
申请号:US15794628
申请日:2017-10-26
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Chang Hoon Jeon , Yong Seok Kim , Jun Hee Lim
Abstract: A semiconductor device includes a memory cell region including memory cells arranged along channel holes, the channel holes being provided on a substrate to extend in a direction perpendicular to an upper surface of the substrate, and a peripheral circuit region disposed outside of the memory cell region and including low voltage transistors and high voltage transistors. The low voltage transistors include first transistors including a first gate dielectric layer and a first gate electrode layer including a metal, and the high voltage transistors include second transistors including a second gate dielectric layer having a dielectric constant lower than a dielectric constant of the first gate dielectric layer, and a second gate electrode layer including polysilicon.
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公开(公告)号:US11963364B2
公开(公告)日:2024-04-16
申请号:US17954844
申请日:2022-09-28
Applicant: Samsung Electronics Co., Ltd.
Inventor: Seok Han Park , Yong Seok Kim , Hui-Jung Kim , Satoru Yamada , Kyung Hwan Lee , Jae Ho Hong , Yoo Sang Hwang
CPC classification number: H10B51/20 , H01L28/40 , H01L29/0673 , H01L29/45 , H01L29/78391 , H01L29/78696 , H10B51/30
Abstract: A semiconductor device is provided. The semiconductor device includes a first stacked structure including a plurality of first insulating patterns and a plurality of first semiconductor patterns alternately stacked on a substrate, the first stacked structure extending in a first direction parallel to an upper surface of the substrate, a first conductive pattern on one side surface of the first stacked structure, the first conductive pattern extending in a second direction crossing the upper surface of the substrate, and a first ferroelectric layer between the first stacked structure and the first conductive pattern, the first ferroelectric layer extending in the second direction, wherein each of the first semiconductor patterns includes a first impurity region, a first channel region and a second impurity region which are sequentially arranged along the first direction.
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