公开(公告)号：US20230207040A1

公开(公告)日：2023-06-29

申请号：US18115132

申请日：2023-02-28

申请人： Samsung Electronics Co., Ltd.

发明人： Kiheung Kim ,  Sanguhn Cha ,  Junhyung Kim ,  Sungchul Park ,  Hyojin Jung ,  Kyung-Soo Ha

IPC分类号： G11C29/42 ,  G11C11/406 ,  G11C29/20 ,  G11C29/44

CPC分类号： G11C29/42 ,  G11C11/40615 ,  G11C29/20 ,  G11C29/44

摘要： A semiconductor memory device includes a memory cell array, an error correction code (ECC) circuit, a fault address register, a scrubbing control circuit and a control logic circuit. The memory cell array includes memory cell rows. The scrubbing control circuit generates scrubbing addresses based on refresh operations performed on the memory cell array. The control logic circuit controls the ECC circuit such that the ECC circuit performs an error detection operation on a plurality of sub-pages in a first memory cell row to count a number of error occurrences, and determines whether to correct a codeword in which an error is detected based on the number of error occurrences. An uncorrected or corrected codeword is written back, and a row address of the first memory cell row may be stored in the fault address register as a row fault address based on the number of error occurrences.

公开(公告)号：US11615861B2

公开(公告)日：2023-03-28

申请号：US17374822

申请日：2021-07-13

申请人： Samsung Electronics Co., Ltd.

发明人： Kiheung Kim ,  Sanguhn Cha ,  Junhyung Kim ,  Sungchul Park ,  Hyojin Jung ,  Kyungsoo Ha

IPC分类号： G11C29/00 ,  G11C29/42 ,  G11C29/20 ,  G11C29/44 ,  G11C29/12

摘要： A semiconductor memory device includes a memory cell array, an error correction code (ECC) circuit, a fault address register and a control logic circuit. The memory cell array includes a plurality of memory cell rows. The scrubbing control circuit generates scrubbing addresses for performing a scrubbing operation on a first memory cell row based on refresh row addresses for refreshing the memory cell rows. The control logic circuit controls the ECC circuit such that the ECC circuit performs an error detection and correction operation on a plurality of sub-pages in the first memory cell row to count a number of error occurrences during a first interval and determines a sub operation in a second interval in the scrubbing operation based on the number of error occurrences in the first memory cell row.

公开(公告)号：US11462292B1

公开(公告)日：2022-10-04

申请号：US17227582

申请日：2021-04-12

申请人： Samsung Electronics Co., Ltd.

发明人： Kiheung Kim ,  Sanguhn Cha ,  Sungrae Kim ,  Sunghye Cho

IPC分类号： G11C29/42 ,  G11C29/44 ,  G11C29/18 ,  H03M13/11 ,  H03M13/15 ,  G11C29/12

摘要： An error correction circuit includes ECC encoder and an ECC decoder. The ECC encoder generates, based on a first main data obtained by selectively shifting data bits of a main data based on a LSB of a row address, a parity data using an ECC and stores a codeword including the main data and the parity data in a target page. The ECC decoder generates a syndrome based on a second main data obtained by selectively shifting data bits of the main data based on the LSB of the row address, the parity data and a parity check matrix based on the ECC, and corrects a single bit error or corrects two bit errors when the two bit errors occur in adjacent two memory cells based on the syndrome. The mis-corrected bit is generated when the multiple error bits are present in the main data.

公开(公告)号：US11416335B2

公开(公告)日：2022-08-16

申请号：US16934677

申请日：2020-07-21

申请人： Samsung Electronics Co., Ltd.

发明人： Sunghye Cho ,  Chanki Kim ,  Kijun Lee ,  Sanguhn Cha ,  Myungkyu Lee

IPC分类号： G06F11/10 ,  H03M13/00 ,  H01L25/065 ,  H01L25/18

摘要： A semiconductor memory device includes a memory cell array, an error correction circuit, an input/output (I/O) gating circuit and a control logic circuit. The memory cell array is coupled to word-line and bit-lines and is divided into sub array blocks. The error correction circuit generates parity data based on main data using an error correction code (ECC). The control logic circuit controls the error correction circuit and the I/O gating circuit based on a command and address. The control logic circuit stores the main data and the parity data in (k+1) target sub array blocks in the second direction among the sub array blocks, and controls the I/O gating circuit such that a portion of the (k+1) target sub array blocks store both of a portion of the main data and a portion of the parity data.

公开(公告)号：US20240339168A1

公开(公告)日：2024-10-10

申请号：US18746565

申请日：2024-06-18

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Sunghye Cho ,  Kiheung Kim ,  Sungrae Kim ,  Junhyung Kim ,  Kijun Lee ,  Myungkyu Lee ,  Changyong Lee ,  Sanguhn Cha

IPC分类号： G11C29/42 ,  G11C11/408 ,  G11C11/4091 ,  G11C29/12 ,  G11C29/44

CPC分类号： G11C29/42 ,  G11C11/4087 ,  G11C11/4091 ,  G11C29/4401 ,  G11C2029/1202 ,  G11C2029/1204

摘要： A memory system includes a memory module having a plurality of memory devices therein. A memory controller is configured to transmit commands and addresses to the memory module in synchronization with a clock, input/output data to and from the memory module in synchronization with a data transfer clock, and perform system error correction operations on data read from the memory module. The plurality of memory devices perform on-die error correction operations, which are different from each other according to a physical location of the stored read data.

公开(公告)号：US11947810B2

公开(公告)日：2024-04-02

申请号：US17743137

申请日：2022-05-12

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Sungrae Kim ,  Hyeran Kim ,  Myungkyu Lee ,  Chisung Oh ,  Kijun Lee ,  Sunghye Cho ,  Sanguhn Cha

IPC分类号： G06F3/06

CPC分类号： G06F3/0619 ,  G06F3/0655 ,  G06F3/0656 ,  G06F3/0679

摘要： A semiconductor memory device includes a memory cell array and a cyclic redundancy check (CRC) engine. The memory cell array includes a plurality of volatile memory cells coupled to respective ones of a plurality of word-lines and respective ones of a plurality of bit-lines. The CRC engine, during a memory operation on the memory cell array, detects an error in a main data and a system parity data provided from a memory controller external to the semiconductor memory device through a link, generates an error flag indicating whether the detected error corresponds to either a first type of error associated with the link or a second type of error associated with the volatile memory cells based on the system parity data and transmit the error flag to the memory controller.

公开(公告)号：US11106535B2

公开(公告)日：2021-08-31

申请号：US16926000

申请日：2020-07-10

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Sunghye Cho ,  Kijun Lee ,  Yeonggeol Song ,  Sungrae Kim ,  Chanki Kim ,  Myungkyu Lee ,  Sanguhn Cha

IPC分类号： G06F11/10 ,  H03M13/15 ,  H03M13/00

摘要： An error correction circuit includes an error correction code (ECC) encoder and an ECC decoder. The ECC encoder generates, based on a main data, a parity data using an ECC represented by a generation matrix and stores a codeword including the main data and the parity data in a target page. The ECC decoder reads the codeword from the target page as a read codeword based on an externally provided address to generate different syndromes based on the read codeword and a parity check matrix which is based on the ECC, and applies the different syndromes to the main data in the read codeword to correct a single bit error when the single bit error exists in the main data or to correct two bit errors when the two bit errors occur in adjacent two memory cells in the target page.

公开(公告)号：US10140176B2

公开(公告)日：2018-11-27

申请号：US15156804

申请日：2016-05-17

申请人： Samsung Electronics Co., Ltd.

发明人： Sanguhn Cha ,  Hoiju Chung ,  Uksong Kang ,  Chulwoo Park

IPC分类号： G11C29/00 ,  G06F11/10 ,  G11C29/52 ,  H03M13/15 ,  G11C29/02 ,  G11C29/42

摘要： An error correcting method of a semiconductor memory device includes receiving first data from outside the semiconductor memory device. First check bits are generated based on the first data and a first parity generator matrix. The first parity generator matrix includes a plurality of columns of bits. The plurality of columns of bits are arranged in a plurality of parity generator matrix groups. An error correcting code (ECC) code word including a plurality of ECC code word groups is stored in the plurality of memory cell groups. Each of the plurality of ECC code word groups have the first data and the first check bits. The plurality of ECC code word groups correspond to the plurality of parity generator matrix groups, respectively. For each parity generator matrix group of the first parity generator matrix, a result value of a bit-by-bit exclusive OR (XOR) operation performed on any two columns included in the parity generator matrix group is equal to a column number of a column that is not included in the parity generator matrix group. Thus, when a first ECC code word group, from among the plurality of ECC code word groups, includes error bits, a miscorrected bit that would be caused by the error bits as a result of performing an error correction operation on the first ECC code word group is located in an ECC code word group other than the first ECC code word group.

公开(公告)号：US20170168931A1

公开(公告)日：2017-06-15

申请号：US15354354

申请日：2016-11-17

申请人： Samsung Electronics Co., Ltd.

发明人： Chankyung Kim ,  Uksong Kang ,  Sanguhn Cha ,  Sungyong Seo ,  Youngjin Cho ,  Seongil O

IPC分类号： G06F12/02 ,  G11C14/00 ,  G11C7/10 ,  G11C11/406 ,  G11C11/4093 ,  G11C11/4096

CPC分类号： G06F12/0871 ,  G06F11/1064 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0853 ,  G06F12/0868 ,  G06F12/0895 ,  G06F2212/1004 ,  G06F2212/1028 ,  G06F2212/205 ,  G06F2212/214 ,  G06F2212/22 ,  G06F2212/313 ,  G06F2212/60 ,  G06F2212/601 ,  G06F2212/7203 ,  G11C5/04 ,  G11C7/1072 ,  G11C11/005 ,  G11C11/4093 ,  G11C16/0483

摘要： A nonvolatile memory module includes at least one nonvolatile memory, at least one nonvolatile memory controller configured to control the nonvolatile memory, at least one dynamic random access memory (DRAM) used as a cache of the at least one nonvolatile memory, data buffers configured to store data exchanged between the at least one DRAM and an external device, and a memory module control device configured to control the nonvolatile memory controller, the at least one DRAM, and the data buffers. The at least one DRAM stores a tag corresponding to cache data and compares the stored tag with input tag information to determine whether to output the cache data.

公开(公告)号：US11366716B2

公开(公告)日：2022-06-21

申请号：US17088900

申请日：2020-11-04

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Yesin Ryu ,  Namsung Kim ,  Sanguhn Cha ,  Jaeyoun Youn ,  Kijun Lee

IPC分类号： G06F11/10 ,  H01L25/065

摘要： A semiconductor memory device including: a buffer die; memory dies stacked on the buffer die; and TSVs, at least one of the memory dies includes: a memory cell array; an error correction code (ECC) engine; an error information register; and a control logic circuit configured to control the ECC engine to perform a read-modify-write operation, wherein the control logic circuit is configured to: record, in the error information register, a first address associated with a first codeword based on the an generation signal and a first syndrome obtained by an ECC decoding; and determine an error attribute of the first codeword based on a change of the first syndrome, recorded in the error information register, based on a plurality of read-modify-write operations.