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    Semiconductor memory devices and methods of operating semiconductor memory devices
    1.
    发明授权
    Semiconductor memory devices and methods of operating semiconductor memory devices 有权

    公开(公告)号：US11626181B2

    公开(公告)日：2023-04-11

    申请号：US17245075

    申请日：2021-04-30

    申请人： Samsung Electronics Co., Ltd.

    发明人： Kiheung Kim ,  Sanguhn Cha ,  Junhyung Kim ,  Sungchul Park ,  Hyojin Jung ,  Kyung-Soo Ha

    IPC分类号： G11C29/42 ,  G11C11/406 ,  G11C29/20 ,  G11C29/44

    摘要： A semiconductor memory device includes a memory cell array, an error correction code (ECC) circuit, a fault address register, a scrubbing control circuit and a control logic circuit. The memory cell array includes memory cell rows. The scrubbing control circuit generates scrubbing addresses based on refresh operations performed on the memory cell array. The control logic circuit controls the ECC circuit such that the ECC circuit performs an error detection operation on a plurality of sub-pages in a first memory cell row to count a number of error occurrences, and determines whether to correct a codeword in which an error is detected based on the number of error occurrences. An uncorrected or corrected codeword is written back, and a row address of the first memory cell row may be stored in the fault address register as a row fault address based on the number of error occurrences.

    Semiconductor memory device and a method of operating the semiconductor memory device
    3.
    发明授权
    Semiconductor memory device and a method of operating the semiconductor memory device 有权

    公开(公告)号：US11545211B2

    公开(公告)日：2023-01-03

    申请号：US17400585

    申请日：2021-08-12

    申请人： SAMSUNG ELECTRONICS CO., LTD.

    发明人： Kiheung Kim ,  Junhyung Kim ,  Sungchul Park ,  Hangyun Jung ,  Hyojin Jung ,  Kyungsoo Ha

    IPC分类号： G11C11/4091 ,  G11C11/408 ,  G06F7/58 ,  G11C11/402

    摘要： A semiconductor memory device includes a memory cell array, a sense amplifier circuit and a random code generator. The memory cell array is divided into a plurality of sub array blocks arranged in a first direction and a second direction crossing the first direction. The sense amplifier circuit is arranged in the second direction with respect to the memory cell array, and includes a plurality of input/output (I/O) sense amplifiers. The random code generator generates a random code which is randomly determined based on a power stabilizing signal and an anti-fuse flag signal. A second group of I/O sense amplifiers selected from among a first group of I/O sense amplifiers performs a data I/O operation by data scrambling data bits of main data. The first group of I/O sense amplifiers correspond to a first group of sub array blocks accessed by an access address.

    SEMICONDUCTOR MEMORY DEVICES AND METHODS OF OPERATING SEMICONDUCTOR MEMORY DEVICES
    4.
    发明申请
    SEMICONDUCTOR MEMORY DEVICES AND METHODS OF OPERATING SEMICONDUCTOR MEMORY DEVICES 有权

    公开(公告)号：US20220093200A1

    公开(公告)日：2022-03-24

    申请号：US17245075

    申请日：2021-04-30

    申请人： Samsung Electronics Co., Ltd.

    发明人： Kiheung Kim ,  Sanguhn Cha ,  Junhyung Kim ,  Sungchul Park ,  Hyojin Jung ,  Kyung-Soo Ha

    IPC分类号： G11C29/42 ,  G11C29/44 ,  G11C29/20 ,  G11C11/406

    摘要： A semiconductor memory device includes a memory cell array, an error correction code (ECC) circuit, a fault address register, a scrubbing control circuit and a control logic circuit. The memory cell array includes memory cell rows. The scrubbing control circuit generates scrubbing addresses based on refresh operations performed on the memory cell array. The control logic circuit controls the ECC circuit such that the ECC circuit performs an error detection operation on a plurality of sub-pages in a first memory cell row to count a number of error occurrences, and determines whether to correct a codeword in which an error is detected based on the number of error occurrences. An uncorrected or corrected codeword is written back , and a row address of the first memory cell row may be stored in the fault address register as a row fault address based on the number of error occurrences.

    Semiconductor memory devices and methods of operating semiconductor memory devices
    6.
    发明授权
    Semiconductor memory devices and methods of operating semiconductor memory devices 有权

    公开(公告)号：US11615861B2

    公开(公告)日：2023-03-28

    申请号：US17374822

    申请日：2021-07-13

    申请人： Samsung Electronics Co., Ltd.

    发明人： Kiheung Kim ,  Sanguhn Cha ,  Junhyung Kim ,  Sungchul Park ,  Hyojin Jung ,  Kyungsoo Ha

    IPC分类号： G11C29/00 ,  G11C29/42 ,  G11C29/20 ,  G11C29/44 ,  G11C29/12

    摘要： A semiconductor memory device includes a memory cell array, an error correction code (ECC) circuit, a fault address register and a control logic circuit. The memory cell array includes a plurality of memory cell rows. The scrubbing control circuit generates scrubbing addresses for performing a scrubbing operation on a first memory cell row based on refresh row addresses for refreshing the memory cell rows. The control logic circuit controls the ECC circuit such that the ECC circuit performs an error detection and correction operation on a plurality of sub-pages in the first memory cell row to count a number of error occurrences during a first interval and determines a sub operation in a second interval in the scrubbing operation based on the number of error occurrences in the first memory cell row.