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公开(公告)号：US12057184B2
公开(公告)日：2024-08-06
申请号：US18164100
申请日：2023-02-03
发明人： Sunghye Cho , Kiheung Kim , Sungrae Kim , Junhyung Kim , Kijun Lee , Myungkyu Lee , Changyong Lee , Sanguhn Cha
IPC分类号： G11C29/42 , G11C11/408 , G11C11/4091 , G11C29/44 , G11C29/12
CPC分类号： G11C29/42 , G11C11/4087 , G11C11/4091 , G11C29/4401 , G11C2029/1202 , G11C2029/1204
摘要： A memory system includes a memory module having a plurality of memory devices therein. A memory controller is configured to transmit commands and addresses to the memory module in synchronization with a clock, input/output data to and from the memory module in synchronization with a data transfer clock, and perform system error correction operations on data read from the memory module. The plurality of memory devices perform on-die error correction operations, which are different from each other according to a physical location of the stored read data.
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公开(公告)号：US20230420033A1
公开(公告)日：2023-12-28
申请号：US18196703
申请日：2023-05-12
发明人： Jongcheol Kim , Kiheung Kim , Taeyoung Oh , Kyungho Lee , Hyongryol Hwang
IPC分类号： G11C11/4078 , G11C11/408 , G11C11/4096 , G11C11/4094
CPC分类号： G11C11/4078 , G11C11/4087 , G11C11/4096 , G11C11/4094
摘要： A semiconductor memory device, including a memory cell array; a row hammer management circuit configured to: count a number of accesses based on an active command, and based on a first command applied after the active command, perform an internal read-update-write operation to read the count data from the count cells of a target memory cell row, and to write updated count data in the count cells of the target memory cell row; and a column decoder configured to: access a first memory cell using a first bit-line; and store data in the first memory cell using a first voltage, or perform an internal write operation to store the count data in the first memory cell using a second voltage greater than the first voltage during an internal write time interval smaller than a reference write time interval.
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公开(公告)号：US11605441B1
公开(公告)日：2023-03-14
申请号：US17461380
申请日：2021-08-30
发明人： Sunghye Cho , Kiheung Kim , Sungrae Kim , Junhyung Kim , Kijun Lee , Myungkyu Lee , Changyong Lee , Sanguhn Cha
IPC分类号： G11C29/42 , G11C29/44 , G11C11/408 , G11C11/4091 , G11C29/12
摘要： A memory system includes a memory module having a plurality of memory devices therein. A memory controller is configured to transmit commands and addresses to the memory module in synchronization with a clock, input/output data to and from the memory module in synchronization with a data transfer clock, and perform system error correction operations on data read from the memory module. The plurality of memory devices perform on-die error correction operations, which are different from each other according to a physical location of the stored read data.
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公开(公告)号：US20230207040A1
公开(公告)日：2023-06-29
申请号：US18115132
申请日：2023-02-28
发明人： Kiheung Kim , Sanguhn Cha , Junhyung Kim , Sungchul Park , Hyojin Jung , Kyung-Soo Ha
IPC分类号： G11C29/42 , G11C11/406 , G11C29/20 , G11C29/44
CPC分类号： G11C29/42 , G11C11/40615 , G11C29/20 , G11C29/44
摘要： A semiconductor memory device includes a memory cell array, an error correction code (ECC) circuit, a fault address register, a scrubbing control circuit and a control logic circuit. The memory cell array includes memory cell rows. The scrubbing control circuit generates scrubbing addresses based on refresh operations performed on the memory cell array. The control logic circuit controls the ECC circuit such that the ECC circuit performs an error detection operation on a plurality of sub-pages in a first memory cell row to count a number of error occurrences, and determines whether to correct a codeword in which an error is detected based on the number of error occurrences. An uncorrected or corrected codeword is written back, and a row address of the first memory cell row may be stored in the fault address register as a row fault address based on the number of error occurrences.
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公开(公告)号：US11615861B2
公开(公告)日：2023-03-28
申请号：US17374822
申请日：2021-07-13
发明人： Kiheung Kim , Sanguhn Cha , Junhyung Kim , Sungchul Park , Hyojin Jung , Kyungsoo Ha
摘要： A semiconductor memory device includes a memory cell array, an error correction code (ECC) circuit, a fault address register and a control logic circuit. The memory cell array includes a plurality of memory cell rows. The scrubbing control circuit generates scrubbing addresses for performing a scrubbing operation on a first memory cell row based on refresh row addresses for refreshing the memory cell rows. The control logic circuit controls the ECC circuit such that the ECC circuit performs an error detection and correction operation on a plurality of sub-pages in the first memory cell row to count a number of error occurrences during a first interval and determines a sub operation in a second interval in the scrubbing operation based on the number of error occurrences in the first memory cell row.
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公开(公告)号：US11462292B1
公开(公告)日：2022-10-04
申请号：US17227582
申请日：2021-04-12
发明人： Kiheung Kim , Sanguhn Cha , Sungrae Kim , Sunghye Cho
摘要： An error correction circuit includes ECC encoder and an ECC decoder. The ECC encoder generates, based on a first main data obtained by selectively shifting data bits of a main data based on a LSB of a row address, a parity data using an ECC and stores a codeword including the main data and the parity data in a target page. The ECC decoder generates a syndrome based on a second main data obtained by selectively shifting data bits of the main data based on the LSB of the row address, the parity data and a parity check matrix based on the ECC, and corrects a single bit error or corrects two bit errors when the two bit errors occur in adjacent two memory cells based on the syndrome. The mis-corrected bit is generated when the multiple error bits are present in the main data.
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7.发明公开公开(公告)号：US20240339168A1
公开(公告)日：2024-10-10
申请号：US18746565
申请日：2024-06-18
发明人： Sunghye Cho , Kiheung Kim , Sungrae Kim , Junhyung Kim , Kijun Lee , Myungkyu Lee , Changyong Lee , Sanguhn Cha
IPC分类号： G11C29/42 , G11C11/408 , G11C11/4091 , G11C29/12 , G11C29/44
CPC分类号： G11C29/42 , G11C11/4087 , G11C11/4091 , G11C29/4401 , G11C2029/1202 , G11C2029/1204
摘要： A memory system includes a memory module having a plurality of memory devices therein. A memory controller is configured to transmit commands and addresses to the memory module in synchronization with a clock, input/output data to and from the memory module in synchronization with a data transfer clock, and perform system error correction operations on data read from the memory module. The plurality of memory devices perform on-die error correction operations, which are different from each other according to a physical location of the stored read data.
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公开(公告)号：US20240038292A1
公开(公告)日：2024-02-01
申请号：US18357204
申请日：2023-07-24
发明人： Kiheung Kim , Taeyoung Oh , Jongcheol Kim , Kyungho Lee , Hyongryol Hwang
IPC分类号： G11C11/4078 , G11C11/4096 , G11C11/4076 , G11C11/406
CPC分类号： G11C11/4078 , G11C11/4096 , G11C11/4076 , G11C11/40622
摘要： A semiconductor memory device includes a memory cell array including a plurality of memory cell rows, a row hammer management circuit and a control logic circuit. The row hammer management circuit stores counted values in count cells of each of the plurality of memory cell rows as count data based on an active command applied to the control logic circuit at a first time point, and performs an internal read-update-write operation to read the count data from the count cells of a target memory cell row from among the plurality of memory cell rows, to update the count data that was read to obtain updated count data, and to write the updated count data in the count cells of the target memory cell row in response to a precharge command applied at a second time point after a first command that is applied to the control logic circuit.
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公开(公告)号：US20230418487A1
公开(公告)日：2023-12-28
申请号：US18136915
申请日：2023-04-20
发明人： Jongcheol Kim , Kiheung Kim , Taeyoung Oh , Kyungho Lee
IPC分类号： G06F3/06
CPC分类号： G06F3/0632 , G06F3/0604 , G06F3/0679
摘要： A semiconductor memory device includes a memory cell array, a row hammer management circuit and a refresh control circuit. The row hammer management circuit automatically stores random count data in count cells of each of a plurality of memory cell rows during a power-up sequence of the semiconductor memory device and determines counted values by counting a number of times of access associated with each of the plurality of memory cell rows in response to an active command from an external memory controller and stores the counted values in the count cells of each of the plurality of memory cell rows as count data. The refresh control circuit receives a hammer address and performs a hammer refresh operation on one or more of the plurality of memory cell rows that are physically adjacent to a memory cell row that corresponds to the hammer address.
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公开(公告)号：US11545211B2
公开(公告)日：2023-01-03
申请号：US17400585
申请日：2021-08-12
发明人： Kiheung Kim , Junhyung Kim , Sungchul Park , Hangyun Jung , Hyojin Jung , Kyungsoo Ha
IPC分类号： G11C11/4091 , G11C11/408 , G06F7/58 , G11C11/402
摘要： A semiconductor memory device includes a memory cell array, a sense amplifier circuit and a random code generator. The memory cell array is divided into a plurality of sub array blocks arranged in a first direction and a second direction crossing the first direction. The sense amplifier circuit is arranged in the second direction with respect to the memory cell array, and includes a plurality of input/output (I/O) sense amplifiers. The random code generator generates a random code which is randomly determined based on a power stabilizing signal and an anti-fuse flag signal. A second group of I/O sense amplifiers selected from among a first group of I/O sense amplifiers performs a data I/O operation by data scrambling data bits of main data. The first group of I/O sense amplifiers correspond to a first group of sub array blocks accessed by an access address.
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