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公开(公告)号：US20250060886A1
公开(公告)日：2025-02-20
申请号：US18805709
申请日：2024-08-15
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Ki-Heung Kim , ChangSik Yoo , Jeongdon Ihm , Hyongryol Hwang
IPC: G06F3/06
Abstract: A memory device includes at least one bank including at least a first sub-bank and a second sub-bank disposed in a wordline direction. The first sub-bank may include a normal data region connected to a plurality of first wordlines and storing normal data, the second sub-bank may include a metadata region connected to a plurality of second wordlines and storing metadata corresponding to the normal data, the plurality of first wordlines may match the plurality of second wordlines to form a plurality of wordline pairs, and the first sub-bank and the second sub-bank may share a row hammer region storing a number of access times to the plurality of wordline pairs.
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公开(公告)号：US20240038292A1
公开(公告)日：2024-02-01
申请号：US18357204
申请日：2023-07-24
Applicant: Samsung Electronics Co., Ltd.
Inventor： Kiheung Kim , Taeyoung Oh , Jongcheol Kim , Kyungho Lee , Hyongryol Hwang
IPC: G11C11/4078 , G11C11/4096 , G11C11/4076 , G11C11/406
CPC classification number: G11C11/4078 , G11C11/4096 , G11C11/4076 , G11C11/40622
Abstract: A semiconductor memory device includes a memory cell array including a plurality of memory cell rows, a row hammer management circuit and a control logic circuit. The row hammer management circuit stores counted values in count cells of each of the plurality of memory cell rows as count data based on an active command applied to the control logic circuit at a first time point, and performs an internal read-update-write operation to read the count data from the count cells of a target memory cell row from among the plurality of memory cell rows, to update the count data that was read to obtain updated count data, and to write the updated count data in the count cells of the target memory cell row in response to a precharge command applied at a second time point after a first command that is applied to the control logic circuit.
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公开(公告)号：US12062404B2
公开(公告)日：2024-08-13
申请号：US18239548
申请日：2023-08-29
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Minho Choi , Jaeseong Lim , Kyungryun Kim , Daehyun Kim , Wonil Bae , Hohyun Shin , Sanghoon Jung , Hyongryol Hwang
Abstract: A voltage trimming circuit including: a first resistance circuit having a first resistance value determined by up codes and down codes; a second resistance circuit having a second resistance value determined by the up codes and the down codes; and a comparator to output a voltage detection signal by comparing a voltage level of a reference voltage trimming node to that of a feedback node, wherein the voltage detection signal adjusts the up and down codes, which increase the first resistance value and decrease the second resistance value when the voltage level of the reference voltage trimming node is higher than that of the feedback node, and adjusts the up and down codes, which decrease the first resistance value and increase the second resistance value when the voltage level of the reference voltage trimming node is lower than that of the feedback node.
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公开(公告)号：US20240221860A1
公开(公告)日：2024-07-04
申请号：US18448346
申请日：2023-08-11
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jongcheol Kim , Taeyoung Oh , Hyongryol Hwang
IPC: G11C29/00
CPC classification number: G11C29/76 , G11C29/789
Abstract: A semiconductor memory device includes a plurality of memory cells partitioned into a plurality of row blocks that are each associated with at least one respective row block identity bit within a portion of a row address. A row decoder is provided, which includes a repair controller having a plurality of fuse boxes therein that correspond to respective ones of the plurality of row blocks and include a first fuse box configured to store a first defective address. The repair controller is configured to: (i) activate a first redundancy word-line, which replaces a first defective word-line designated by the first defective address, in response to comparing a first access address with the first defective address output from the first fuse box, during a first mode, and (ii) activate a second redundancy word-line, which replaces a first edge word-line designated by the first access address, in response to comparing the first access address with a first reset address output from the first fuse box, during a second mode.
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公开(公告)号：US20240028221A1
公开(公告)日：2024-01-25
申请号：US18302276
申请日：2023-04-18
Applicant: Samsung Electronics Co., Ltd.
Inventor： Kyungho Lee , Kiheung Kim , Taeyoung Oh , Jongcheol Kim , Hyongryol Hwang
IPC: G06F3/06
CPC classification number: G06F3/0623 , G06F3/0653 , G06F3/0673
Abstract: A semiconductor memory device includes a memory cell array including a plurality of memory cell rows and a row hammer management circuit. The row hammer management circuit stores counted values in count cells of each of the plurality of memory cell rows as count data, and performs an internal read-update-write operation to read the count data from the count cells of a target memory cell row from among the plurality of memory cell rows, to update the count data that was read to obtain updated count data, and to write the updated count data in the count cells of the target memory cell row. The row hammer management circuit includes a hammer address queue. The row hammer management circuit changes the updated count data randomly, based on an event signal indicating a state change of the hammer address queue.
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Patent Agency Ranking
公开(公告)号：US20250061939A1
公开(公告)日：2025-02-20
申请号：US18806022
申请日：2024-08-15
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Ki-Heung Kim , ChangSik Yoo , Jeongdon Ihm , Hyongryol Hwang
IPC: G11C11/4096 , G11C11/408
Abstract: A memory device includes at least one bank including a first sub-bank and a second sub-bank disposed in a wordline direction. The first sub-bank may store normal data and may be connected to a plurality of first wordlines, the second sub-bank may store metadata corresponding to the normal data and may be connected to a plurality of second wordlines, and metadata for normal data corresponding to each of the first wordlines may be stored in each of second wordlines, respectively corresponding to the first wordlines.
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公开(公告)号：US20250028456A1
公开(公告)日：2025-01-23
申请号：US18907760
申请日：2024-10-07
Applicant: Samsung Electronics Co., Ltd.
Inventor： Kyungho Lee , Kiheung Kim , Taeyoung Oh , Jongcheol Kim , Hyongryol Hwang
IPC: G06F3/06
Abstract: A semiconductor memory device includes a memory cell array including a plurality of memory cell rows and a row hammer management circuit. The row hammer management circuit stores counted values in count cells of each of the plurality of memory cell rows as count data, and performs an internal read-update-write operation to read the count data from the count cells of a target memory cell row from among the plurality of memory cell rows, to update the count data that was read to obtain updated count data, and to write the updated count data in the count cells of the target memory cell row. The row hammer management circuit includes a hammer address queue. The row hammer management circuit changes the updated count data randomly, based on an event signal indicating a state change of the hammer address queue.
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公开(公告)号：US20240404586A1
公开(公告)日：2024-12-05
申请号：US18651072
申请日：2024-04-30
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Ki-Heung Kim , Taeyoung Oh , Hyongryol Hwang
IPC: G11C11/4097 , G11C11/408 , G11C11/4091
Abstract: A memory device includes a bank connected to a plurality of wordlines, a first global input and output (GIO) line, and a second GIO line formed to have a larger length than the first GIO line in a column direction. One of the first GIO line and the second GIO line may be allocated for metadata.
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9.发明公开公开(公告)号：US20240289058A1
公开(公告)日：2024-08-29
申请号：US18590324
申请日：2024-02-28
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Ki-Heung KIM , Taeyoung Oh , Taekwoon Kim , Jinseong Yun , Yoonjae Jeong , Hyongryol Hwang
IPC: G06F3/06
CPC classification number: G06F3/0659 , G06F3/0604 , G06F3/0683
Abstract: A method of operating a memory module that communicates with a memory controller includes: entering a one-time programmable (OTP) addressing mode based on an OTP command received from the memory controller; determining whether a guard key sequence is satisfied based on a plurality of mode register commands received from the memory controller; and programming, based on a determination that the guard key sequence is satisfied, a unique identifier (ID), corresponding to a target memory device, into the target memory device, among a plurality of memory devices included in the memory module.
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公开(公告)号：US11776644B2
公开(公告)日：2023-10-03
申请号：US17591987
申请日：2022-02-03
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Minho Choi , Jaeseong Lim , Kyungryun Kim , Daehyun Kim , Wonil Bae , Hohyun Shin , Sanghoon Jung , Hyongryol Hwang
Abstract: A voltage trimming circuit including: a first resistance circuit having a first resistance value determined by up codes and down codes; a second resistance circuit having a second resistance value determined by the up codes and the down codes; and a comparator to output a voltage detection signal by comparing a voltage level of a reference voltage trimming node to that of a feedback node, wherein the voltage detection signal adjusts the up and down codes, which increase the first resistance value and decrease the second resistance value when the voltage level of the reference voltage trimming node is higher than that of the feedback node, and adjusts the up and down codes, which decrease the first resistance value and increase the second resistance value when the voltage level of the reference voltage trimming node is lower than that of the feedback node.
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