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公开(公告)号：US20240038292A1
公开(公告)日：2024-02-01
申请号：US18357204
申请日：2023-07-24
发明人： Kiheung Kim , Taeyoung Oh , Jongcheol Kim , Kyungho Lee , Hyongryol Hwang
IPC分类号： G11C11/4078 , G11C11/4096 , G11C11/4076 , G11C11/406
CPC分类号： G11C11/4078 , G11C11/4096 , G11C11/4076 , G11C11/40622
摘要： A semiconductor memory device includes a memory cell array including a plurality of memory cell rows, a row hammer management circuit and a control logic circuit. The row hammer management circuit stores counted values in count cells of each of the plurality of memory cell rows as count data based on an active command applied to the control logic circuit at a first time point, and performs an internal read-update-write operation to read the count data from the count cells of a target memory cell row from among the plurality of memory cell rows, to update the count data that was read to obtain updated count data, and to write the updated count data in the count cells of the target memory cell row in response to a precharge command applied at a second time point after a first command that is applied to the control logic circuit.
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2.发明公开公开(公告)号：US20240289058A1
公开(公告)日：2024-08-29
申请号：US18590324
申请日：2024-02-28
发明人： Ki-Heung KIM , Taeyoung Oh , Taekwoon Kim , Jinseong Yun , Yoonjae Jeong , Hyongryol Hwang
IPC分类号： G06F3/06
CPC分类号： G06F3/0659 , G06F3/0604 , G06F3/0683
摘要： A method of operating a memory module that communicates with a memory controller includes: entering a one-time programmable (OTP) addressing mode based on an OTP command received from the memory controller; determining whether a guard key sequence is satisfied based on a plurality of mode register commands received from the memory controller; and programming, based on a determination that the guard key sequence is satisfied, a unique identifier (ID), corresponding to a target memory device, into the target memory device, among a plurality of memory devices included in the memory module.
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公开(公告)号：US11776644B2
公开(公告)日：2023-10-03
申请号：US17591987
申请日：2022-02-03
发明人： Minho Choi , Jaeseong Lim , Kyungryun Kim , Daehyun Kim , Wonil Bae , Hohyun Shin , Sanghoon Jung , Hyongryol Hwang
摘要： A voltage trimming circuit including: a first resistance circuit having a first resistance value determined by up codes and down codes; a second resistance circuit having a second resistance value determined by the up codes and the down codes; and a comparator to output a voltage detection signal by comparing a voltage level of a reference voltage trimming node to that of a feedback node, wherein the voltage detection signal adjusts the up and down codes, which increase the first resistance value and decrease the second resistance value when the voltage level of the reference voltage trimming node is higher than that of the feedback node, and adjusts the up and down codes, which decrease the first resistance value and increase the second resistance value when the voltage level of the reference voltage trimming node is lower than that of the feedback node.
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4.发明公开公开(公告)号：US20240345944A1
公开(公告)日：2024-10-17
申请号：US18634559
申请日：2024-04-12
发明人： KI-HEUNG KIM , Taeyoung Oh , Taekwoon Kim , Jinseong Yun , Yoonjae Jeong , Hyongryol Hwang
IPC分类号： G06F12/02
CPC分类号： G06F12/0223 , G06F2212/202
摘要： A method of operating a memory configured to communicate with a memory controller, the method includes: temporarily storing a unique identification (ID) for each of a plurality of memory devices included in the memory to each of the plurality of memory devices; selecting a target memory device from among the plurality of memory devices; and permanently or substantially permanently programming, in the target memory device, a unique ID corresponding to the target memory device.
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公开(公告)号：US20230420033A1
公开(公告)日：2023-12-28
申请号：US18196703
申请日：2023-05-12
发明人： Jongcheol Kim , Kiheung Kim , Taeyoung Oh , Kyungho Lee , Hyongryol Hwang
IPC分类号： G11C11/4078 , G11C11/408 , G11C11/4096 , G11C11/4094
CPC分类号： G11C11/4078 , G11C11/4087 , G11C11/4096 , G11C11/4094
摘要： A semiconductor memory device, including a memory cell array; a row hammer management circuit configured to: count a number of accesses based on an active command, and based on a first command applied after the active command, perform an internal read-update-write operation to read the count data from the count cells of a target memory cell row, and to write updated count data in the count cells of the target memory cell row; and a column decoder configured to: access a first memory cell using a first bit-line; and store data in the first memory cell using a first voltage, or perform an internal write operation to store the count data in the first memory cell using a second voltage greater than the first voltage during an internal write time interval smaller than a reference write time interval.
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公开(公告)号：US20230410925A1
公开(公告)日：2023-12-21
申请号：US18239548
申请日：2023-08-29
发明人： Minho Choi , Jaeseong Lim , Kyungryun Kim , Daehyun Kim , Wonil Bae , Hohyun Shin , Sanghoon Jung , Hyongryol Hwang
摘要： A voltage trimming circuit including: a first resistance circuit having a first resistance value determined by up codes and down codes; a second resistance circuit having a second resistance value determined by the up codes and the down codes; and a comparator to output a voltage detection signal by comparing a voltage level of a reference voltage trimming node to that of a feedback node, wherein the voltage detection signal adjusts the up and down codes, which increase the first resistance value and decrease the second resistance value when the voltage level of the reference voltage trimming node is higher than that of the feedback node, and adjusts the up and down codes, which decrease the first resistance value and increase the second resistance value when the voltage level of the reference voltage trimming node is lower than that of the feedback node.
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公开(公告)号：US20220284975A1
公开(公告)日：2022-09-08
申请号：US17591987
申请日：2022-02-03
发明人： Minho Choi , Jaeseong Lim , Kyungryun Kim , Daehyun Kim , Wonil Bae , Hohyun Shin , Sanghoon Jung , Hyongryol Hwang
摘要： A voltage trimming circuit including: a first resistance circuit having a first resistance value determined by up codes and down codes; a second resistance circuit having a second resistance value determined by the up codes and the down codes; and a comparator to output a voltage detection signal by comparing a voltage level of a reference voltage trimming node to that of a feedback node, wherein the voltage detection signal adjusts the up and down codes, which increase the first resistance value and decrease the second resistance value when the voltage level of the reference voltage trimming node is higher than that of the feedback node, and adjusts the up and down codes, which decrease the first resistance value and increase the second resistance value when the voltage level of the reference voltage trimming node is lower than that of the feedback node.
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公开(公告)号：US12062404B2
公开(公告)日：2024-08-13
申请号：US18239548
申请日：2023-08-29
发明人： Minho Choi , Jaeseong Lim , Kyungryun Kim , Daehyun Kim , Wonil Bae , Hohyun Shin , Sanghoon Jung , Hyongryol Hwang
摘要： A voltage trimming circuit including: a first resistance circuit having a first resistance value determined by up codes and down codes; a second resistance circuit having a second resistance value determined by the up codes and the down codes; and a comparator to output a voltage detection signal by comparing a voltage level of a reference voltage trimming node to that of a feedback node, wherein the voltage detection signal adjusts the up and down codes, which increase the first resistance value and decrease the second resistance value when the voltage level of the reference voltage trimming node is higher than that of the feedback node, and adjusts the up and down codes, which decrease the first resistance value and increase the second resistance value when the voltage level of the reference voltage trimming node is lower than that of the feedback node.
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公开(公告)号：US20240221860A1
公开(公告)日：2024-07-04
申请号：US18448346
申请日：2023-08-11
发明人： Jongcheol Kim , Taeyoung Oh , Hyongryol Hwang
IPC分类号： G11C29/00
CPC分类号： G11C29/76 , G11C29/789
摘要： A semiconductor memory device includes a plurality of memory cells partitioned into a plurality of row blocks that are each associated with at least one respective row block identity bit within a portion of a row address. A row decoder is provided, which includes a repair controller having a plurality of fuse boxes therein that correspond to respective ones of the plurality of row blocks and include a first fuse box configured to store a first defective address. The repair controller is configured to: (i) activate a first redundancy word-line, which replaces a first defective word-line designated by the first defective address, in response to comparing a first access address with the first defective address output from the first fuse box, during a first mode, and (ii) activate a second redundancy word-line, which replaces a first edge word-line designated by the first access address, in response to comparing the first access address with a first reset address output from the first fuse box, during a second mode.
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公开(公告)号：US20240028221A1
公开(公告)日：2024-01-25
申请号：US18302276
申请日：2023-04-18
发明人： Kyungho Lee , Kiheung Kim , Taeyoung Oh , Jongcheol Kim , Hyongryol Hwang
IPC分类号： G06F3/06
CPC分类号： G06F3/0623 , G06F3/0653 , G06F3/0673
摘要： A semiconductor memory device includes a memory cell array including a plurality of memory cell rows and a row hammer management circuit. The row hammer management circuit stores counted values in count cells of each of the plurality of memory cell rows as count data, and performs an internal read-update-write operation to read the count data from the count cells of a target memory cell row from among the plurality of memory cell rows, to update the count data that was read to obtain updated count data, and to write the updated count data in the count cells of the target memory cell row. The row hammer management circuit includes a hammer address queue. The row hammer management circuit changes the updated count data randomly, based on an event signal indicating a state change of the hammer address queue.
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