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    SEMICONDUCTOR MEMORY DEVICE AND METHODS OF OPERATION
    1.
    发明公开
    SEMICONDUCTOR MEMORY DEVICE AND METHODS OF OPERATION 审中-公开

    公开(公告)号：US20230185460A1

    公开(公告)日：2023-06-15

    申请号：US18076628

    申请日：2022-12-07

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kiheung Kim ,  Taeyoung Oh ,  Hyeran Kim ,  Sungyong Cho ,  Kyungsoo Ha

    IPC: G06F3/06

    CPC classification number: G06F3/0619 ,  G06F3/0653 ,  G06F3/0659 ,  G06F3/0673

    Abstract: A semiconductor memory device includes a memory cell array, a row hammer management circuit and a control logic circuit. The memory cell array includes a plurality of memory cell rows. The row hammer management circuit counts the number of instances of access of each of the memory cell rows, such as in response to the receipt of an active command, to store the counted values in count cells of each of the memory cell rows as count data and, in response to a first command, initiates an internal read-update-write operation to read the count data, to update the read count data, and to write the updated count data in the count cells. The control logic circuit may performs an internal write operation to write the updated count data in the count cells during a second write time interval that is smaller than a first write time interval associated with a normal write operation.

    SEMICONDUCTOR MEMORY DEVICES
    3.
    发明公开
    SEMICONDUCTOR MEMORY DEVICES 审中-公开

    公开(公告)号：US20240012712A1

    公开(公告)日：2024-01-11

    申请号：US18169769

    申请日：2023-02-15

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jongcheol Kim ,  Hyunsung Shin ,  Hohyun Shin ,  Taeyoung Oh ,  Kyungsoo Ha

    IPC: G06F11/10 ,  G06F3/06 ,  G11C11/4096 ,  G11C11/408

    CPC classification number: G06F11/1068 ,  G06F3/0619 ,  G06F3/0659 ,  G06F3/0679 ,  G11C11/4096 ,  G11C11/4082

    Abstract: A semiconductor memory device includes a memory cell array, a data input/output (I/O) buffer, an I/O gating circuit and a control logic circuit. The memory cell array includes a plurality of sub array blocks arranged in a first direction and a second direction. The data I/O buffer exchanges user data with a memory controller through I/O pads. The I/O gating circuit is connected to the data I/O buffer through data buses and connected to the memory cell array through data I/O lines, and programs mapping relationship between the sub array blocks and the I/O pads, based on a mapping control signal such that uncorrectable errors that are detected by an error correction code engine in the memory controller are reduced. The control logic circuit generates the mapping control signal based on identifier information indicating a type of a central processing unit of the memory controller.

    SEMICONDUCTOR MEMORY DEVICES
    8.
    发明申请
    SEMICONDUCTOR MEMORY DEVICES 有权

    公开(公告)号：US20240371417A1

    公开(公告)日：2024-11-07

    申请号：US18771859

    申请日：2024-07-12

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jongcheol Kim ,  Hyunsung Shin ,  Hohyun Shin ,  Taeyoung Oh ,  Kyungsoo Ha

    IPC: G11C7/10 ,  G06F3/06 ,  G06F11/10 ,  G11C11/408 ,  G11C11/4093 ,  G11C11/4096

    Abstract: A semiconductor memory device includes a memory cell array, a data input/output (I/O) buffer, an I/O gating circuit and a control logic circuit. The memory cell array includes a plurality of sub array blocks arranged in a first direction and a second direction. The data VO buffer exchanges user data with a memory controller through I/O pads. The I/O gating circuit is connected to the data I/O buffer through data buses and connected to the memory cell array through data I/O lines, and programs mapping relationship between the sub array blocks and the I/O pads, based on a mapping control signal such that uncorrectable errors that are detected by an error correction code engine in the memory controller are reduced. The control logic circuit generates the mapping control signal based on identifier information indicating a type of a central processing unit of the memory controller.

    Voltage generator and semiconductor device including the same
    10.
    发明授权
    Voltage generator and semiconductor device including the same 有权

    公开(公告)号：US12040704B2

    公开(公告)日：2024-07-16

    申请号：US18063777

    申请日：2022-12-09

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sungju Lee ,  Kyungsoo Ha

    IPC: H02M3/07 ,  H02M1/00 ,  G11C5/14

    CPC classification number: H02M3/07 ,  H02M1/0025 ,  H02M1/0041 ,  G11C5/145

    Abstract: A voltage generator includes a charge pump circuit including a first charge pump having a plurality of first pumping capacitors, and a second charge pump having a plurality of second pumping capacitors having a capacitance different from a capacitance of each of the plurality of first pumping capacitors. The charge pump circuit is configured to supply a power supply voltage to a power mesh. The voltage generator further includes a controller configured to output a control signal based on a target level of the power supply voltage, and an oscillator configured to output a clock signal to the charge pump circuit. The oscillator outputs the clock signal to one of the first charge pump and the second charge pump based on the control signal.

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