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公开(公告)号：US12073910B2
公开(公告)日：2024-08-27
申请号：US18169769
申请日：2023-02-15
发明人： Jongcheol Kim , Hyunsung Shin , Hohyun Shin , Taeyoung Oh , Kyungsoo Ha
IPC分类号： G11C7/10 , G06F3/06 , G11C11/4093 , G11C11/4096 , G06F11/10 , G11C11/408
CPC分类号： G11C7/1012 , G06F3/0619 , G11C11/4093 , G11C11/4096 , G06F3/0659 , G06F3/0679 , G06F11/1068 , G11C11/4082 , G11C2207/005
摘要： A semiconductor memory device includes a memory cell array, a data input/output (I/O) buffer, an I/O gating circuit and a control logic circuit. The memory cell array includes a plurality of sub array blocks arranged in a first direction and a second direction. The data I/O buffer exchanges user data with a memory controller through I/O pads. The I/O gating circuit is connected to the data I/O buffer through data buses and connected to the memory cell array through data I/O lines, and programs mapping relationship between the sub array blocks and the I/O pads, based on a mapping control signal such that uncorrectable errors that are detected by an error correction code engine in the memory controller are reduced. The control logic circuit generates the mapping control signal based on identifier information indicating a type of a central processing unit of the memory controller.
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公开(公告)号：US20230420033A1
公开(公告)日：2023-12-28
申请号：US18196703
申请日：2023-05-12
发明人： Jongcheol Kim , Kiheung Kim , Taeyoung Oh , Kyungho Lee , Hyongryol Hwang
IPC分类号： G11C11/4078 , G11C11/408 , G11C11/4096 , G11C11/4094
CPC分类号： G11C11/4078 , G11C11/4087 , G11C11/4096 , G11C11/4094
摘要： A semiconductor memory device, including a memory cell array; a row hammer management circuit configured to: count a number of accesses based on an active command, and based on a first command applied after the active command, perform an internal read-update-write operation to read the count data from the count cells of a target memory cell row, and to write updated count data in the count cells of the target memory cell row; and a column decoder configured to: access a first memory cell using a first bit-line; and store data in the first memory cell using a first voltage, or perform an internal write operation to store the count data in the first memory cell using a second voltage greater than the first voltage during an internal write time interval smaller than a reference write time interval.
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公开(公告)号：US20240038292A1
公开(公告)日：2024-02-01
申请号：US18357204
申请日：2023-07-24
发明人： Kiheung Kim , Taeyoung Oh , Jongcheol Kim , Kyungho Lee , Hyongryol Hwang
IPC分类号： G11C11/4078 , G11C11/4096 , G11C11/4076 , G11C11/406
CPC分类号： G11C11/4078 , G11C11/4096 , G11C11/4076 , G11C11/40622
摘要： A semiconductor memory device includes a memory cell array including a plurality of memory cell rows, a row hammer management circuit and a control logic circuit. The row hammer management circuit stores counted values in count cells of each of the plurality of memory cell rows as count data based on an active command applied to the control logic circuit at a first time point, and performs an internal read-update-write operation to read the count data from the count cells of a target memory cell row from among the plurality of memory cell rows, to update the count data that was read to obtain updated count data, and to write the updated count data in the count cells of the target memory cell row in response to a precharge command applied at a second time point after a first command that is applied to the control logic circuit.
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公开(公告)号：US20230418487A1
公开(公告)日：2023-12-28
申请号：US18136915
申请日：2023-04-20
发明人： Jongcheol Kim , Kiheung Kim , Taeyoung Oh , Kyungho Lee
IPC分类号： G06F3/06
CPC分类号： G06F3/0632 , G06F3/0604 , G06F3/0679
摘要： A semiconductor memory device includes a memory cell array, a row hammer management circuit and a refresh control circuit. The row hammer management circuit automatically stores random count data in count cells of each of a plurality of memory cell rows during a power-up sequence of the semiconductor memory device and determines counted values by counting a number of times of access associated with each of the plurality of memory cell rows in response to an active command from an external memory controller and stores the counted values in the count cells of each of the plurality of memory cell rows as count data. The refresh control circuit receives a hammer address and performs a hammer refresh operation on one or more of the plurality of memory cell rows that are physically adjacent to a memory cell row that corresponds to the hammer address.
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公开(公告)号：US20240221860A1
公开(公告)日：2024-07-04
申请号：US18448346
申请日：2023-08-11
发明人： Jongcheol Kim , Taeyoung Oh , Hyongryol Hwang
IPC分类号： G11C29/00
CPC分类号： G11C29/76 , G11C29/789
摘要： A semiconductor memory device includes a plurality of memory cells partitioned into a plurality of row blocks that are each associated with at least one respective row block identity bit within a portion of a row address. A row decoder is provided, which includes a repair controller having a plurality of fuse boxes therein that correspond to respective ones of the plurality of row blocks and include a first fuse box configured to store a first defective address. The repair controller is configured to: (i) activate a first redundancy word-line, which replaces a first defective word-line designated by the first defective address, in response to comparing a first access address with the first defective address output from the first fuse box, during a first mode, and (ii) activate a second redundancy word-line, which replaces a first edge word-line designated by the first access address, in response to comparing the first access address with a first reset address output from the first fuse box, during a second mode.
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公开(公告)号：US20240028221A1
公开(公告)日：2024-01-25
申请号：US18302276
申请日：2023-04-18
发明人： Kyungho Lee , Kiheung Kim , Taeyoung Oh , Jongcheol Kim , Hyongryol Hwang
IPC分类号： G06F3/06
CPC分类号： G06F3/0623 , G06F3/0653 , G06F3/0673
摘要： A semiconductor memory device includes a memory cell array including a plurality of memory cell rows and a row hammer management circuit. The row hammer management circuit stores counted values in count cells of each of the plurality of memory cell rows as count data, and performs an internal read-update-write operation to read the count data from the count cells of a target memory cell row from among the plurality of memory cell rows, to update the count data that was read to obtain updated count data, and to write the updated count data in the count cells of the target memory cell row. The row hammer management circuit includes a hammer address queue. The row hammer management circuit changes the updated count data randomly, based on an event signal indicating a state change of the hammer address queue.
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公开(公告)号：US20240012712A1
公开(公告)日：2024-01-11
申请号：US18169769
申请日：2023-02-15
发明人： Jongcheol Kim , Hyunsung Shin , Hohyun Shin , Taeyoung Oh , Kyungsoo Ha
IPC分类号： G06F11/10 , G06F3/06 , G11C11/4096 , G11C11/408
CPC分类号： G06F11/1068 , G06F3/0619 , G06F3/0659 , G06F3/0679 , G11C11/4096 , G11C11/4082
摘要： A semiconductor memory device includes a memory cell array, a data input/output (I/O) buffer, an I/O gating circuit and a control logic circuit. The memory cell array includes a plurality of sub array blocks arranged in a first direction and a second direction. The data I/O buffer exchanges user data with a memory controller through I/O pads. The I/O gating circuit is connected to the data I/O buffer through data buses and connected to the memory cell array through data I/O lines, and programs mapping relationship between the sub array blocks and the I/O pads, based on a mapping control signal such that uncorrectable errors that are detected by an error correction code engine in the memory controller are reduced. The control logic circuit generates the mapping control signal based on identifier information indicating a type of a central processing unit of the memory controller.
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公开(公告)号：US12118221B2
公开(公告)日：2024-10-15
申请号：US18136915
申请日：2023-04-20
发明人： Jongcheol Kim , Kiheung Kim , Taeyoung Oh , Kyungho Lee
CPC分类号： G06F3/0632 , G06F3/0604 , G06F3/0679
摘要： A semiconductor memory device includes a memory cell array, a row hammer management circuit and a refresh control circuit. The row hammer management circuit automatically stores random count data in count cells of each of a plurality of memory cell rows during a power-up sequence of the semiconductor memory device and determines counted values by counting a number of times of access associated with each of the plurality of memory cell rows in response to an active command from an external memory controller and stores the counted values in the count cells of each of the plurality of memory cell rows as count data. The refresh control circuit receives a hammer address and performs a hammer refresh operation on one or more of the plurality of memory cell rows that are physically adjacent to a memory cell row that corresponds to the hammer address.
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