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    INTEGRATED CIRCUIT DEVICE INCLUDING VERTICAL MEMORY
    5.
    发明申请
    INTEGRATED CIRCUIT DEVICE INCLUDING VERTICAL MEMORY 有权

    公开(公告)号：US20220208269A1

    公开(公告)日：2022-06-30

    申请号：US17698627

    申请日：2022-03-18

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： KWANYONG KIM ,  SUNIL SHIM ,  WONSEOK CHO

    IPC: G11C16/08 ,  G11C16/04

    Abstract: An integrated circuit device includes a plurality of word lines, a string selection line structure stacked on the plurality of word lines, and a plurality of channel structures extending in a vertical direction through the plurality of word lines and the string selection line structure. The string selection line structure includes a string selection bent line including a lower horizontal extension portion extending in a horizontal direction at a first level higher than the plurality of word lines, an upper horizontal extension portion extending in the horizontal direction at a second level higher than the first level, and a vertical extension portion connected between the lower horizontal extension portion and the upper horizontal extension portion.

    SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME
    6.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME 有权

    公开(公告)号：US20210091104A1

    公开(公告)日：2021-03-25

    申请号：US16874159

    申请日：2020-05-14

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： SANGHOON JEONG ,  SANGJUN HONG ,  SUNIL SHIM ,  KYUNGHYUN KIM ,  CHANGSUP MUN

    IPC: H01L27/11556 ,  H01L27/11582 ,  G11C5/02

    Abstract: A semiconductor memory device includes a stack structure comprising horizontal electrodes sequentially stacked on a substrate including a cell array region and an extension region and horizontal insulating layers between the horizontal electrodes. The semiconductor memory device may further include vertical structures that penetrate the stack structure, a first one of the vertical structures being on the cell array region and a second one of the vertical structures being on the extension region. Each of the vertical structures includes a channel layer, and a tunneling insulating layer, a charge storage layer and a blocking insulating layer which are sequentially stacked on a sidewall of the channel layer. The charge storage layer of the first vertical structure includes charge storage patterns spaced apart from each other in a direction perpendicular to a top surface of the substrate with the horizontal insulating layers interposed therebetween. The charge storage layer of the second vertical structure extends along sidewalls of the horizontal electrodes and sidewalls of the horizontal insulating layers.

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