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公开(公告)号：US11749536B2
公开(公告)日：2023-09-05
申请号：US17355478
申请日：2021-06-23
发明人： Byoungdeog Choi , Jangseop Kim
IPC分类号： H01L21/311 , H01L21/033 , H01L21/56
CPC分类号： H01L21/565 , H01L21/0337 , H01L21/31116 , H01L21/31144
摘要： A method of fabricating a semiconductor may include forming on a substrate a mold structure including a mold layer, a buffer layer, and a support layer, performing on the mold structure an anisotropic etching process to form a plurality of through holes in the mold structure, and forming a plurality of bottom electrodes in the through holes. The buffer layer has a nitrogen content amount that increases as approaching the support layer from the mold layer. The buffer layer has an oxygen content amount that increases as approaching the mold layer from the support layer.
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公开(公告)号：US11211447B2
公开(公告)日：2021-12-28
申请号：US16282548
申请日：2019-02-22
发明人： Hyukwoo Kwon , Ha-Young Yi , Byoungdeog Choi , Seongmin Choo
IPC分类号： H01L27/108 , H01L49/02 , H01L21/311
摘要： A semiconductor device includes a substrate, a bottom electrode on the substrate, a first support layer on the substrate next to a sidewall of the bottom electrode, a dielectric layer covering the sidewall and a top surface of the bottom electrode, and a top electrode on the dielectric layer. The bottom electrode includes a first part having a plurality of protrusions that protrude from a sidewall of the first part. The first part of the bottom electrode may be on the first support layer.
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公开(公告)号：US10910261B2
公开(公告)日：2021-02-02
申请号：US16577429
申请日：2019-09-20
发明人： Byoungdeog Choi , JungWoo Seo , Sangyeon Han , Hyun-Woo Chung , Hongrae Kim , Yoosang Hwang
IPC分类号： H01L27/108 , H01L21/768 , H01L23/498 , H01L27/22 , H01L27/24 , H01L45/00 , H01L23/522 , H01L23/528 , H01L23/532
摘要： A semiconductor device includes bit line structures on a substrate, the bit line structures extending along a first direction and being spaced apart from each other along a second direction perpendicular to the first direction, contact plugs spaced apart from each other along the first direction and being on active regions of the substrate between adjacent bit line structures, a linear spacer on each longitudinal sidewall of a bit line structure, landing pads on the contact plugs, respectively, the landing pads being electrically connected to the contact plugs, respectively, and landing pads that are adjacent to each other along the first direction being offset with respect to each other along the second direction, as viewed in a top view, a conductive pad between each of the contact plugs and a corresponding active region, a vertical axes of the conductive pad and corresponding active region being horizontally offset.
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公开(公告)号：US20210118705A1
公开(公告)日：2021-04-22
申请号：US16882494
申请日：2020-05-24
发明人： Byoungdeog Choi , Dongyoung Kim
IPC分类号： H01L21/67 , H01L21/02 , H01L21/768
摘要： An integrated circuit (IC) device includes a lower electrode including a main portion having a sidewall with at least one step portion, and a top portion having a width less than that of the main portion in a lateral direction. An upper support pattern contacts the top portion of the lower electrode. The upper support pattern includes a seam portion. To manufacture an IC device, a mold pattern and an upper sacrificial support pattern through which a plurality of holes pass are formed on a substrate. A plurality of lower electrodes are formed inside the plurality of holes. A peripheral space is formed on the mold pattern. An enlarged peripheral space is formed by reducing a width and a height of the top portion. An upper support pattern is formed to fill the enlarged peripheral space.
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公开(公告)号：US09570448B2
公开(公告)日：2017-02-14
申请号：US15191552
申请日：2016-06-24
发明人： Youn-Seok Choi , Young-min Ko , Honggun Kim , Jongmyeong Lee , Byoungdeog Choi
IPC分类号： H01L21/20 , H01L27/108 , H01L21/311 , H01L49/02
CPC分类号： H01L28/90 , H01L21/31111 , H01L21/31116 , H01L21/31144 , H01L27/10852
摘要： A method for manufacturing a semiconductor device includes forming a storage node hole passing through an upper support layer, a bowing prevention layer and an upper mold layer using a dry etching process, forming a lower electrode in the storage node hole, patterning the upper support layer and the bowing prevention layer to expose a portion of the upper mold layer, removing the upper mold layer and at least a portion of the bowing prevention layer using a first wet etching process, and sequentially forming a dielectric layer and an upper electrode that cover the lower electrode. An etch rate of the bowing prevention layer may be substantially equal to an etch rate of the upper support layer during the dry etching process. An etch rate of the bowing prevention layer may be higher than an etch rate of the upper support layer during the first wet etching process.
摘要翻译： 一种半导体装置的制造方法，其特征在于，包括：通过干式蚀刻工序形成穿过上支撑层，弓形防止层和上模层的存储节点孔，在所述存储节点孔中形成下电极，使所述上支撑层 以及所述弯曲防止层，以暴露所述上模层的一部分，使用第一湿蚀刻工艺去除所述上模层和所述防弓层的至少一部分，并且顺序地形成覆盖所述上模具层的电介质层和上电极 下电极。 弯曲防止层的蚀刻速率可以基本上等于在干蚀刻工艺期间上支撑层的蚀刻速率。 在第一湿法蚀刻工艺期间，防弓层的蚀刻速率可高于上支撑层的蚀刻速率。
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公开(公告)号：US20210082844A1
公开(公告)日：2021-03-18
申请号：US16848194
申请日：2020-04-14
发明人： Dongwoo Kim , Hyukwoo Kwon , Seongmin Choo , Byoungdeog Choi
IPC分类号： H01L23/00
摘要： An integrated circuit (IC) device includes a lower electrode formed on a substrate, and an upper support structure disposed around the lower electrode and supporting the lower electrode. The upper support structure includes an upper support pattern surrounding the lower electrode and extending in a lateral direction parallel to the substrate, the upper support pattern having a hole through which the lower electrode passes, and an upper spacer support pattern between the upper support pattern and the lower electrode inside the hole and having an outer sidewall in contact with the upper support pattern and an inner sidewall in contact with the lower electrode, wherein a width of the upper spacer support pattern in the lateral direction decreases in a direction toward the substrate. To manufacture an IC device, an upper support pattern is formed on a substrate. An upper spacer support film is formed to cover a sidewall and a top surface of the upper support pattern. A plurality of lower electrodes are formed inside a plurality of holes formed in the upper support pattern. Portions of the upper spacer support film are removed to form a plurality of upper spacer support patterns between the upper support pattern and the lower electrodes, respectively.
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公开(公告)号：US20170076974A1
公开(公告)日：2017-03-16
申请号：US15343712
申请日：2016-11-04
发明人： Byoungdeog Choi , JungWoo Seo , Sangyeon Han , Hyun-Woo Chung , Hongrae Kim , Yoosang Hwang
IPC分类号： H01L21/768 , H01L23/532 , H01L27/22 , H01L27/108 , H01L27/24 , H01L23/528 , H01L23/522
CPC分类号： H01L21/7682 , H01L21/76816 , H01L21/76877 , H01L21/76897 , H01L23/498 , H01L23/5226 , H01L23/528 , H01L23/5329 , H01L27/10814 , H01L27/10855 , H01L27/10876 , H01L27/228 , H01L27/2436 , H01L27/2463 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/143 , H01L45/144 , H01L45/146 , H01L45/147 , H01L45/16 , H01L2221/1063 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes a pair of line patterns disposed on a substrate. A contact plug is disposed between the pair of line patterns and an air gap is disposed between the contact plug and the line patterns. A landing pad extends from a top end of the contact plug to cover a first part of the air gap and an insulating layer is disposed on a second part of the air gap, which is not covered by the landing pad.
摘要翻译： 半导体器件包括设置在衬底上的一对线图案。 接触插头设置在一对线路图案之间，并且气隙设置在接触插塞和线路图案之间。 着陆垫从接触塞的顶端延伸以覆盖气隙的第一部分，并且绝缘层设置在气隙的第二部分上，其未被着陆垫覆盖。
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公开(公告)号：US11810947B2
公开(公告)日：2023-11-07
申请号：US17536524
申请日：2021-11-29
发明人： Hyukwoo Kwon , Ha-young Yi , Byoungdeog Choi , Seongmin Choo
IPC分类号： H01L45/00 , H01L49/02 , H01L21/311 , H10B12/00
CPC分类号： H01L28/90 , H01L21/31116 , H01L21/31144 , H01L28/92 , H10B12/033
摘要： A semiconductor device includes a substrate, a bottom electrode on the substrate, a first support layer on the substrate next to a sidewall of the bottom electrode, a dielectric layer covering the sidewall and a top surface of the bottom electrode, and a top electrode on the dielectric layer. The bottom electrode includes a first part having a plurality of protrusions that protrude from a sidewall of the first part. The first part of the bottom electrode may be on the first support layer.
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公开(公告)号：US11764107B2
公开(公告)日：2023-09-19
申请号：US17144226
申请日：2021-01-08
发明人： Byoungdeog Choi , JungWoo Seo , Sangyeon Han , Hyun-Woo Chung , Hongrae Kim , Yoosang Hwang
IPC分类号： H01L21/768 , H01L23/498 , H10B12/00 , H10B61/00 , H10B63/00 , H10N70/00 , H01L23/522 , H01L23/528 , H01L23/532 , H10N70/20
CPC分类号： H01L21/7682 , H01L21/76816 , H01L21/76877 , H01L21/76897 , H01L23/498 , H01L23/528 , H01L23/5226 , H01L23/5329 , H10B12/315 , H10B61/22 , H10B63/30 , H10B63/80 , H10N70/011 , H10N70/8825 , H10N70/8828 , H10N70/8833 , H10N70/8836 , H01L2221/1063 , H01L2924/0002 , H10B12/0335 , H10B12/053 , H10N70/20 , H10N70/231 , H10N70/826 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes a pair of line patterns disposed on a substrate. A contact plug is disposed between the pair of line patterns and an air gap is disposed between the contact plug and the line patterns. A landing pad extends from a top end of the contact plug to cover a first part of the air gap and an insulating layer is disposed on a second part of the air gap, which is not covered by the landing pad.
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10.发明授权公开(公告)号：US11114398B2
公开(公告)日：2021-09-07
申请号：US16848194
申请日：2020-04-14
发明人： Dongwoo Kim , Hyukwoo Kwon , Seongmin Choo , Byoungdeog Choi
IPC分类号： H01L23/00
摘要： An integrated circuit (IC) device includes a lower electrode formed on a substrate, and an upper support structure disposed around the lower electrode and supporting the lower electrode. The upper support structure includes an upper support pattern surrounding the lower electrode and extending in a lateral direction parallel to the substrate, the upper support pattern having a hole through which the lower electrode passes, and an upper spacer support pattern between the upper support pattern and the lower electrode inside the hole and having an outer sidewall in contact with the upper support pattern and an inner sidewall in contact with the lower electrode, wherein a width of the upper spacer support pattern in the lateral direction decreases in a direction toward the substrate. To manufacture an IC device, an upper support pattern is formed on a substrate. An upper spacer support film is formed to cover a sidewall and a top surface of the upper support pattern. A plurality of lower electrodes are formed inside a plurality of holes formed in the upper support pattern. Portions of the upper spacer support film are removed to form a plurality of upper spacer support patterns between the upper support pattern and the lower electrodes, respectively.
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