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    Semiconductor memory device having reduced variation of erasing and writing voltages supplied to each memory array
    1.
    发明授权
    Semiconductor memory device having reduced variation of erasing and writing voltages supplied to each memory array 失效
    具有减小提供给每个存储器阵列的擦除和写入电压的变化的半导体存储器件

    公开(公告)号：US5936886A

    公开(公告)日：1999-08-10

    申请号：US953995

    申请日：1997-10-20

    Applicant: Ryosuke Fujio ,  Mitsuru Sekiguchi

    Inventor： Ryosuke Fujio ,  Mitsuru Sekiguchi

    IPC: H01L21/8247 ,  G11C16/30 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C11/34

    CPC classification number: G11C16/30

    Abstract: In a semiconductor memory device comprising a plurality of memory arrays, the memory array is given a predetermined potential from a terminal via a reference line. Further, a plurality of source switches are connected to the memory arrays and the reference line. The source switches selectively transfer the predetermined potential to each of the memory arrays. In this case, each of the source switches includes a transistor having an electrical ability which is determined by a length of the reference line between each source switch and the terminal.When the transistor is formed by a MOS transistor, the above electrical ability is specified by the ON resistance of the MOS transistor. The MOS transistors are designed so that the ON resistance becomes lower as the length of the reference line between the source switch and the terminal becomes longer. At any rate, a substantially constant voltage is supplied to each of the memory arrays irrelevant of the length of the reference line between each source switch and the terminal.

    Abstract translation: 在包括多个存储器阵列的半导体存储器件中，存储器阵列经由参考线从端子被给予预定电位。 此外，多个源极开关连接到存储器阵列和参考线。 源开关选择性地将预定电位传输到每个存储器阵列。 在这种情况下，每个源极开关包括具有由每个源极开关和端子之间的参考线​​的长度决定的电能的晶体管。 当晶体管由MOS晶体管形成时，上述电能由MOS晶体管的导通电阻指定。 MOS晶体管被设计成使得当源极开关和端子之间的参考线​​的长度变长时，导通电阻变低。 无论如何，与每个源极开关和端子之间的参考线​​的长度无关地，向每个存储器阵列提供基本恒定的电压。

    Nonvolatile semiconductor memory device
    5.
    发明授权
    Nonvolatile semiconductor memory device 失效
    非易失性半导体存储器件

    公开(公告)号：US06407954B2

    公开(公告)日：2002-06-18

    申请号：US09781829

    申请日：2001-02-12

    Applicant: Kazuhisa Ninomiya ,  Mitsuru Sekiguchi

    Inventor： Kazuhisa Ninomiya ,  Mitsuru Sekiguchi

    IPC: G11C700

    CPC classification number: G11C16/3459 ,  G11C16/10 ,  G11C16/3454

    Abstract: A nonvolatile semiconductor memory device comprises a plurality of sectors each having a plurality of memory cell arrays, a controller which responds to an address signal and a control signal to activate at least one of the sectors; and a plurality of data comparing circuits provided in the memory cell arrays, respectively, the data comparing circuits each which latches a write data to be written the respective memory cell arrays and compares the write data latched and a data read out from the respective memory cell arrays to produce a comparison result. The controller activates all of the sectors when the control signal has a first logic level regardless of levels of the address signal so that write data is written into the memory cell arrays of the sectors activated. The controller activates the sectors in sequence in response to changing levels of the address signal when the control signal has a second logic level to output the comparison results from the data comparing circuits in sequence.

    Abstract translation: 非易失性半导体存储器件包括多个扇区，每个扇区各自具有多个存储单元阵列;响应地址信号的控制器和控制信号以激活至少一个扇区; 以及分别设置在存储单元阵列中的多个数据比较电路，每个数据比较电路锁存写入数据以写入各个存储单元阵列的数据比较电路，并比较锁存的写入数据和从各个存储单元读出的数据 数组产生比较结果。 当控制信号具有第一逻辑电平而无论地址信号的电平如何，控制器激活所有扇区，使得写入数据被写入被激活的扇区的存储单元阵列中。 当控制信号具有第二逻辑电平时，响应于地址信号的变化电平，控制器按顺序激活扇区，从而顺序地从数据比较电路输出比较结果。

    Nonvolatile semiconductor memory device
    6.
    发明授权
    Nonvolatile semiconductor memory device 失效
    非易失性半导体存储器件

    公开(公告)号：US06272045B1

    公开(公告)日：2001-08-07

    申请号：US09527825

    申请日：2000-03-17

    Applicant: Mitsuru Sekiguchi

    Inventor： Mitsuru Sekiguchi

    IPC: G11C1604

    CPC classification number: G11C16/10 ,  G11C16/26

    Abstract: A nonvolatile semiconductor memory device has writing signal line selecting transistors for applying writing signals to memory elements, respectively, reading signal line selecting transistors for delivering reading signals from the memory elements, respectively, and bit line selecting transistors connected between the writing signal line selecting transistors or the reading signal line selecting transistors and the memory elements, for selecting bit lines of each of the memory elements.

    Abstract translation: 非易失性半导体存储器件分别具有写入信号线选择晶体管，用于分别向存储元件施加写入信号，分别读取用于从存储元件传送读取信号的信号线选择晶体管，以及连接在写入信号线选择晶体管 或读取信号线选择晶体管和存储器元件，用于选择每个存储元件的位线。

    RADIATION DETECTOR
    7.
    发明申请
    RADIATION DETECTOR 失效
    辐射探测器

    公开(公告)号：US20120001282A1

    公开(公告)日：2012-01-05

    申请号：US13256052

    申请日：2010-02-23

    Applicant: Narito Goto ,  Mitsuru Sekiguchi

    Inventor： Narito Goto ,  Mitsuru Sekiguchi

    IPC: H01L31/115

    CPC classification number: G01T1/2018 ,  C09K11/628 ,  G21K4/00 ,  G21K2004/06

    Abstract: A radiation detector of a compact size and producing almost no image defect is disclosed, comprising a first radiation-transmissive substrate, a first adhesive layer, a second radiation-transmissive substrate, a scintillator layer and an output substrate provided with a photoelectric conversion element layer which are provided sequentially in this order, wherein an arrangement region of the scintillator layer in a planar direction of the layer includes an arrangement region of the photoelectric conversion element layer in a planar direction of the layer and an arrangement region of the first substrate in a planar direction of the substrate, and the arrangement region of the first substrate includes the arrangement region of the photoelectric conversion element layer; and when the arrangement region of the scintillator layer is divided to plural areas, a coefficient of variation of filling factor is 20% or less which is defined as a standard deviation of filling factor of phosphor of the plural areas, divided by an average value of the filling factor.

    Abstract translation: 公开了一种紧凑尺寸并且几乎不产生图像缺陷的辐射检测器，包括第一辐射透射基板，第一粘合层，第二辐射透射基板，闪烁体层和设置有光电转换元件层的输出基板 其顺序地依次提供，其中闪烁体层在层的平面方向上的布置区域包括在该层的平面方向上的光电转换元件层的布置区域和第一基板的布置区域 基板的平面方向，第一基板的配置区域包括光电转换元件层的配置区域; 并且当闪烁体层的排列区域被划分为多个区域时，填充系数的变化系数为20％以下，其被定义为多个区域的荧光体的填充系数的标准偏差除以平均值 填充因子。

    SCINTILLATOR PLATE, MANUFACTURING METHOD OF THE SAME AND RADIATION IMAGE SENSOR
    9.
    发明申请
    SCINTILLATOR PLATE, MANUFACTURING METHOD OF THE SAME AND RADIATION IMAGE SENSOR 有权
    扫描板，其制造方法和辐射图像传感器

    公开(公告)号：US20080054181A1

    公开(公告)日：2008-03-06

    申请号：US11846312

    申请日：2007-08-28

    Applicant: Masashi Kondo ,  Yasushi Nagata ,  Mitsuru Sekiguchi

    Inventor： Masashi Kondo ,  Yasushi Nagata ,  Mitsuru Sekiguchi

    IPC: G01T1/20

    CPC classification number: G01T1/202

    Abstract: A scintillator plate comprising: (i) a radiation transmissive substrate; (ii) a light absorbing layer formed on the substrate, the light absorbing layer absorbing light of a prescribed wavelength range; and (iii) a scintillator layer formed on the light absorbing layer, the scintillator layer converting radiation to the light having a wavelength absorbable to the light absorbing layer.

    Abstract translation: 一种闪烁体板，包括：（i）辐射透射基底; （ii）形成在所述基板上的光吸收层，所述光吸收层吸收规定波长范围的光; 和（iii）形成在光吸收层上的闪烁体层，所述闪烁体层将辐射转换成具有可吸收光吸收层的波长的光。

    Method for making semiconductor device containing low carbon film for interconnect structures
    10.
    发明授权
    Method for making semiconductor device containing low carbon film for interconnect structures 有权
    制造用于互连结构的含有低碳薄膜的半导体器件的方法

    公开(公告)号：US06333255B1

    公开(公告)日：2001-12-25

    申请号：US09137150

    申请日：1998-08-20

    Applicant: Mitsuru Sekiguchi

    Inventor： Mitsuru Sekiguchi

    IPC: H01L214763

    CPC classification number: H01L21/76885 ,  H01L21/7682 ,  H01L23/5222 ,  H01L23/53238 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A lower carbon film as a provisional film, a lower SiO2 film and an upper carbon film are formed, and then trenches having a wiring pattern are formed in the upper carbon film. Next, contact holes are formed through the lower carbon film and the lower SiO2 film. Then, wires and plugs are formed by filling in the trenches and contact holes with a barrier metal film and a Cu alloy film. After these process steps are repeatedly performed several times, a dummy opening is formed to extend downward through the uppermost SiO2 film. Thereafter, the carbon films are removed by performing ashing with oxygen introduced through the dummy opening. As a result, gas layers are formed to surround the wires and plugs. In this manner, a highly reliable gas-dielectric interconnect structure can be obtained by performing simple process steps.

    Abstract translation: 形成作为临时膜的低碳膜，下部SiO 2膜和上部碳膜，然后在上部碳膜中形成具有布线图案的沟槽。 接下来，通过下部碳膜和下部SiO 2膜形成接触孔。 然后，通过用阻挡金属膜和Cu合金膜填充沟槽和接触孔来形成电线和插头。 在这些处理步骤重复进行几次之后，形成虚拟开口以向下延伸通过最上面的SiO 2膜。 此后，通过经由虚拟开口引入的氧进行灰化除去碳膜。 结果，形成气体层以包围电线和插头。 以这种方式，通过执行简单的工艺步骤可以获得高度可靠的气体 - 电介质互连结构。

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