公开(公告)号：US5936886A

公开(公告)日：1999-08-10

申请号：US953995

申请日：1997-10-20

Applicant: Ryosuke Fujio ,  Mitsuru Sekiguchi

Inventor： Ryosuke Fujio ,  Mitsuru Sekiguchi

IPC: H01L21/8247 ,  G11C16/30 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C11/34

CPC classification number: G11C16/30

Abstract: In a semiconductor memory device comprising a plurality of memory arrays, the memory array is given a predetermined potential from a terminal via a reference line. Further, a plurality of source switches are connected to the memory arrays and the reference line. The source switches selectively transfer the predetermined potential to each of the memory arrays. In this case, each of the source switches includes a transistor having an electrical ability which is determined by a length of the reference line between each source switch and the terminal.When the transistor is formed by a MOS transistor, the above electrical ability is specified by the ON resistance of the MOS transistor. The MOS transistors are designed so that the ON resistance becomes lower as the length of the reference line between the source switch and the terminal becomes longer. At any rate, a substantially constant voltage is supplied to each of the memory arrays irrelevant of the length of the reference line between each source switch and the terminal.

Abstract translation: 在包括多个存储器阵列的半导体存储器件中，存储器阵列经由参考线从端子被给予预定电位。 此外，多个源极开关连接到存储器阵列和参考线。 源开关选择性地将预定电位传输到每个存储器阵列。 在这种情况下，每个源极开关包括具有由每个源极开关和端子之间的参考线​​的长度决定的电能的晶体管。 当晶体管由MOS晶体管形成时，上述电能由MOS晶体管的导通电阻指定。 MOS晶体管被设计成使得当源极开关和端子之间的参考线​​的长度变长时，导通电阻变低。 无论如何，与每个源极开关和端子之间的参考线​​的长度无关地，向每个存储器阵列提供基本恒定的电压。

公开(公告)号：US06195288B1

公开(公告)日：2001-02-27

申请号：US09566882

申请日：2000-05-08

Applicant: Ryosuke Fujio ,  Kazuo Watanabe

Inventor： Ryosuke Fujio ,  Kazuo Watanabe

IPC: G11C1606

CPC classification number: G11C16/28

Abstract: A nonvolatile semiconductor memory device disclosed herein includes: a reference cell held in an ON-state; a reference cell held in an OFF-state; a driving transistor which is turned ON by a signal for reading out data from a memory cell, to supply a current to the memory cell; driving transistors which have a same construction and characteristics as the driving transistor and also which are turned ON by that signal to supply a current to the reference cells; and a sense-amplifier which has a first input terminal supplied with an output voltage of the driving transistor and a second input terminal supplied with an average (VRon+VRoff)/2 of output voltages VRon and VRoff of the driving transistors respectively.

Abstract translation: 本文公开的非易失性半导体存储器件包括：保持在ON状态的参考单元; 保持在OFF状态的参考单元; 通过用于从存储单元读出数据的信号导通的驱动晶体管，向存储单元提供电流; 驱动晶体管，其具有与驱动晶体管相同的结构和特性，并且通过该信号导通，以向参考单元提供电流; 以及感测放大器，其具有被提供有驱动晶体管的输出电压的第一输入端和分别被提供有驱动晶体管的输出电压VRon和VRoff的平均值（VRon + VRoff）/ 2的第二输入端。

公开(公告)号：US06189081B1

公开(公告)日：2001-02-13

申请号：US08862373

申请日：1997-05-23

Applicant: Ryosuke Fujio

Inventor： Ryosuke Fujio

IPC: G06F1202

CPC classification number: G06F3/0616 ,  G06F3/064 ,  G06F3/0679 ,  G06F12/0246 ,  Y02D10/13

Abstract: In a non-volatile semiconductor storage, at the time of a data writing, the size of the data to be written is compared with the size of an erase block and/or the size of a writable storage unit in the erase block. The data having the size corresponding to the size of the erase block is written into a writable erase block, and the data having the size smaller than the size of the erase block is written into the writable storage unit(s), so that a storing area optimum to the size of the data to be written is allocated.

Abstract translation: 在非易失性半导体存储器中，在数据写入时，将要写入的数据的大小与擦除块中的擦除块的大小和/或可写存储单元的大小进行比较。 具有与擦除块的大小相对应的大小的数据被写入可写擦除块，并且具有小于擦除块大小的尺寸的数据被写入可写存储单元中，从而存储 分配对要写入的数据的大小最佳的面积。

公开(公告)号：US6147909A

公开(公告)日：2000-11-14

申请号：US330081

申请日：1999-06-11

Applicant: Ryosuke Fujio

Inventor： Ryosuke Fujio

IPC: G11C16/06 ,  G11C5/14 ,  G11C16/00 ,  G11C16/10 ,  G11C16/12 ,  G11C16/34 ,  G11C8/00

CPC classification number: G11C16/3445 ,  G11C16/10 ,  G11C16/12 ,  G11C16/344 ,  G11C5/145

Abstract: It is an object of the invention to provide an EEPROM, in which the third positive potential for erase verify is supplied from a negative potential generating circuit for supplying a negative or ground potential to a word line. The EEPROM is composed of a P potential supply circuit for respectively supplying a potential to sources of P channel transistors in invertors, which are respectively connected with word lines, a N potential supply circuit for respectively supplying a potential to sources of N channel transistors in the invertors, a read/write decision circuit for deciding whether the EEPROM operates in a read or write mode, and an erase decision circuit for deciding whether the EEPROM operates in an erase mode or not.

Abstract translation: 本发明的目的是提供一种EEPROM，其中用于擦除验证的第三正电位从用于向字线提供负电位或接地电位的负电位发生电路提供。 EEPROM由P电位电源电路构成，该P电位电路分别向分别与字线连接的反相器的P沟道晶体管的源极提供电位，N电位供给电路用于分别在N沟道晶体管的源极 逆变器，用于判定EEPROM是以读取还是写入模式操作的读/写判定电路，以及用于判定EEPROM是否以擦除模式操作的擦除判定电路。