公开(公告)号：US10366914B2

公开(公告)日：2019-07-30

申请号：US15861363

申请日：2018-01-03

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hideki Makiyama

IPC: H01L21/762 ,  H01L29/66 ,  H01L21/311 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/06 ,  H01L27/12 ,  H01L21/84

Abstract: In a manufacturing method for a semiconductor device formed over an SOI substrate, a first epitaxial layer is partially formed over an outer circumference end of a first semiconductor layer in a wide active region. Then, a second epitaxial layer is formed over each of the first semiconductor layers in a narrow active region and the wide active region. Thereby, a second semiconductor layer configured by a laminated body of the first semiconductor layer and the first and second epitaxial layers is formed in the wide active region and a third semiconductor layer configured by a laminated body of the first semiconductor layer and the second epitaxial layer is formed in the narrow active region.

公开(公告)号：US09978839B2

公开(公告)日：2018-05-22

申请号：US15628925

申请日：2017-06-21

Applicant: Renesas Electronics Corporation

Inventor： Yoshiki Yamamoto ,  Hideki Makiyama ,  Toshiaki Iwamatsu ,  Takaaki Tsunomura

IPC: H01L21/00 ,  H01L29/10 ,  H01L29/78 ,  H01L29/06 ,  H01L21/74 ,  H01L29/66 ,  H01L21/265 ,  H01L21/8238 ,  H01L21/84

CPC classification number: H01L29/1083 ,  H01L21/265 ,  H01L21/74 ,  H01L21/76897 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/41783 ,  H01L29/4238 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/66537 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66742 ,  H01L29/66757 ,  H01L29/66772 ,  H01L29/7824 ,  H01L29/7833 ,  H01L29/78606 ,  H01L29/78621 ,  H01L29/78651 ,  H01L29/78654

Abstract: Occurrence of short-channel characteristics and parasitic capacitance of a MOSFET on a SOI substrate is prevented.A sidewall having a stacked structure obtained by sequentially stacking a silicon oxide film and a nitride film is formed on a side wall of a gate electrode on the SOI substrate. Subsequently, after an epitaxial layer is formed beside the gate electrode, and then, the nitride film is removed. Then, an impurity is implanted into an upper surface of the semiconductor substrate with using the gate electrode and the epitaxial layer as a mask, so that a halo region is formed in only a region of the upper surface of the semiconductor substrate which is right below a vicinity of both ends of the gate electrode.

公开(公告)号：US09024386B2

公开(公告)日：2015-05-05

申请号：US13678103

申请日：2012-11-15

Applicant: Renesas Electronics Corporation

Inventor： Katsuyuki Horita ,  Toshiaki Iwamatsu ,  Hideki Makiyama ,  Yoshiki Yamamoto

IPC: H01L21/00 ,  H01L29/78 ,  H01L21/48 ,  H01L21/84 ,  H01L27/02 ,  H01L27/12 ,  H01L21/768 ,  H01L29/786 ,  H01L21/74

CPC classification number: H01L21/84 ,  H01L21/28008 ,  H01L21/283 ,  H01L21/31111 ,  H01L21/486 ,  H01L21/743 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76895 ,  H01L21/76897 ,  H01L27/0207 ,  H01L27/1203 ,  H01L29/66568 ,  H01L29/78 ,  H01L29/78648 ,  H01L29/78654 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Characteristics of a semiconductor device are improved. A semiconductor device of the present invention includes: (a) a MISFET arranged in an active region formed of a semiconductor region surrounded by an element isolation region; and (b) an insulating layer arranged below the active region. Further, the semiconductor device includes: (c) a p-type semiconductor region arranged below the active region so as to interpose the insulating layer; and (d) an n-type semiconductor region whose conductivity type is opposite to the p-type, arranged below the p-type semiconductor region. And, the p-type semiconductor region includes a connection region extending from below the insulating layer, and the p-type semiconductor region and a gate electrode of the MISFET are connected to each other by a shared plug which is an integrally-formed conductive film extending from above the gate electrode to above the connection region.

Abstract translation: 提高了半导体器件的特性。 本发明的半导体器件包括：（a）布置在由元件隔离区包围的半导体区域形成的有源区中的MISFET; 和（b）布置在有源区下方的绝缘层。 此外，半导体器件包括：（c）布置在有源区下方以插入绝缘层的p型半导体区域; 和（d）布置在p型半导体区域下方的导电类型与p型相反的n型半导体区域。 并且，p型半导体区域包括从绝缘层的下方延伸的连接区域，并且MIS型的p型半导体区域和栅极电极通过作为一体形成的导电膜的共享插头彼此连接 从栅电极上方延伸到连接区域的上方。

公开(公告)号：US08941178B2

公开(公告)日：2015-01-27

申请号：US13747537

申请日：2013-01-23

Applicant: Renesas Electronics Corporation

Inventor： Yoshiki Yamamoto ,  Hideki Makiyama ,  Toshiaki Iwamatsu ,  Takaaki Tsunomura

IPC: H01L27/12 ,  H01L29/786 ,  H01L29/66

CPC classification number: H01L29/1083 ,  H01L21/265 ,  H01L21/74 ,  H01L21/76897 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/41783 ,  H01L29/4238 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/66537 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66742 ,  H01L29/66757 ,  H01L29/66772 ,  H01L29/7824 ,  H01L29/7833 ,  H01L29/78606 ,  H01L29/78621 ,  H01L29/78651 ,  H01L29/78654

Abstract: Occurrence of short-channel characteristics and parasitic capacitance of a MOSFET on a SOI substrate is prevented.A sidewall having a stacked structure obtained by sequentially stacking a silicon oxide film and a nitride film is formed on a side wall of a gate electrode on the SOI substrate. Subsequently, after an epitaxial layer is formed beside the gate electrode, and then, the nitride film is removed. Then, an impurity is implanted into an upper surface of the semiconductor substrate with using the gate electrode and the epitaxial layer as a mask, so that a halo region is formed in only a region of the upper surface of the semiconductor substrate which is right below a vicinity of both ends of the gate electrode.

Abstract translation: 防止在SOI衬底上发生MOSFET的短沟道特性和寄生电容。 在SOI衬底上的栅电极的侧壁上形成具有通过依次层叠氧化硅膜和氮化物膜而获得的堆叠结构的侧壁。 随后，在栅极旁边形成外延层之后，去除氮化物膜。 然后，使用栅电极和外延层作为掩模，将杂质注入到半导体衬底的上表面中，使得仅在半导体衬底的上表面的正下方形成晕圈区域 栅电极的两端附近。

公开(公告)号：US11658211B2

公开(公告)日：2023-05-23

申请号：US17224743

申请日：2021-04-07

Applicant: Renesas Electronics Corporation

Inventor： Yoshiki Yamamoto ,  Hideki Makiyama ,  Toshiaki Iwamatsu ,  Takaaki Tsunomura

IPC: H01L21/82 ,  H01L29/08 ,  H01L29/10 ,  H01L29/786 ,  H01L29/66 ,  H01L27/12 ,  H01L29/417 ,  H01L29/423 ,  H01L29/78 ,  H01L21/768 ,  H01L21/8238 ,  H01L21/84 ,  H01L21/265 ,  H01L29/06 ,  H01L21/74 ,  H01L21/8234

CPC classification number: H01L29/1083 ,  H01L21/265 ,  H01L21/74 ,  H01L21/76897 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/41783 ,  H01L29/4238 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/6681 ,  H01L29/66477 ,  H01L29/66537 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66628 ,  H01L29/66742 ,  H01L29/66757 ,  H01L29/66772 ,  H01L29/7824 ,  H01L29/7833 ,  H01L29/78606 ,  H01L29/78621 ,  H01L29/78651 ,  H01L29/78654

Abstract: Occurrence of short-channel characteristics and parasitic capacitance of a MOSFET on a SOI substrate is prevented.
A sidewall having a stacked structure obtained by sequentially stacking a silicon oxide film and a nitride film is formed on a side wall of a gate electrode on the SOI substrate. Subsequently, after an epitaxial layer is formed beside the gate electrode, and then, the nitride film is removed. Then, an impurity is implanted into an upper surface of the semiconductor substrate with using the gate electrode and the epitaxial layer as a mask, so that a halo region is formed in only a region of the upper surface of the semiconductor substrate which is right below a vicinity of both ends of the gate electrode.

公开(公告)号：US11562897B1

公开(公告)日：2023-01-24

申请号：US17369643

申请日：2021-07-07

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hideki Makiyama

IPC: H01L21/02 ,  H01L21/762

Abstract: A wafer having a semiconductor substrate including a peripheral region and a central region, an insulating layer and a semiconductor layer is prepared first. Next, a plurality of trenches penetrating through the semiconductor layer and the insulating layer and reaching an inside of the semiconductor substrate are formed. Next, an inside of each of the plurality of trenches is filled with an insulating film, so that a plurality of element isolating portions is formed. Next, in the central region, the semiconductor layer exposed from a resist pattern is removed. The end portion closest to the outer edge of the semiconductor substrate among ends of the resist pattern used for removing the semiconductor layer in the central region is formed so as to be positioned closer to the outer edge of the semiconductor substrate than a position of the end portion closest to the outer edge of the semiconductor substrate among ends of the resist pattern used for forming the trenches.

公开(公告)号：US10263012B2

公开(公告)日：2019-04-16

申请号：US16040305

申请日：2018-07-19

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hideki Makiyama ,  Yoshiki Yamamoto

IPC: H01L27/12 ,  H01L21/762 ,  H01L21/84 ,  H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L21/8238

Abstract: The semiconductor integrated circuit device has a hybrid substrate structure which includes both of an SOI structure and a bulk structure on the side of the device plane of a semiconductor substrate. In the device, the height of a gate electrode of an SOI type MISFET is higher than that of a gate electrode of a bulk type MISFET with respect to the device plane.

公开(公告)号：US09484433B2

公开(公告)日：2016-11-01

申请号：US14929646

申请日：2015-11-02

Applicant: Renesas Electronics Corporation

Inventor： Yoshiki Yamamoto ,  Hideki Makiyama ,  Toshiaki Iwamatsu ,  Takaaki Tsunomura

IPC: H01L21/00 ,  H01L29/66 ,  H01L29/786 ,  H01L27/12 ,  H01L29/417 ,  H01L29/423 ,  H01L29/78 ,  H01L21/768 ,  H01L29/08 ,  H01L21/8238 ,  H01L21/84 ,  H01L21/265

CPC classification number: H01L29/1083 ,  H01L21/265 ,  H01L21/74 ,  H01L21/76897 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/41783 ,  H01L29/4238 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/66537 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66742 ,  H01L29/66757 ,  H01L29/66772 ,  H01L29/7824 ,  H01L29/7833 ,  H01L29/78606 ,  H01L29/78621 ,  H01L29/78651 ,  H01L29/78654

Abstract: Occurrence of short-channel characteristics and parasitic capacitance of a MOSFET on a SOI substrate is prevented.A sidewall having a stacked structure obtained by sequentially stacking a silicon oxide film and a nitride film is formed on a side wall of a gate electrode on the SOI substrate. Subsequently, after an epitaxial layer is formed beside the gate electrode, and then, the nitride film is removed. Then, an impurity is implanted into an upper surface of the semiconductor substrate with using the gate electrode and the epitaxial layer as a mask, so that a halo region is formed in only a region of the upper surface of the semiconductor substrate which is right below a vicinity of both ends of the gate electrode.

Abstract translation: 在SOI衬底上的栅电极的侧壁上形成具有通过依次层叠氧化硅膜和氮化物膜而获得的堆叠结构的侧壁。 随后，在栅极旁边形成外延层之后，去除氮化物膜。 然后，使用栅电极和外延层作为掩模将杂质注入到半导体衬底的上表面中，使得仅在半导体衬底的上表面的正下方形成晕圈区域 栅电极的两端附近。

公开(公告)号：US09460936B2

公开(公告)日：2016-10-04

申请号：US14856382

申请日：2015-09-16

Applicant: Renesas Electronics Corporation

Inventor： Yoshiki Yamamoto ,  Hideki Makiyama ,  Takaaki Tsunomura ,  Toshiaki Iwamatsu

IPC: H01L21/32 ,  H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L29/786 ,  H01L29/08

CPC classification number: H01L21/32 ,  H01L29/0847 ,  H01L29/42376 ,  H01L29/42384 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/78 ,  H01L29/7834 ,  H01L29/7836 ,  H01L29/7848 ,  H01L29/786 ,  H01L29/78618 ,  H01L29/78627

Abstract: The semiconductor device has a gate electrode GE formed on a substrate via a gate insulating film GI and a source/drain semiconductor layer EP1 formed on the substrate. The upper surface of the semiconductor layer EP1 is positioned higher than the upper surface of the substrate straight below the gate electrode GE. And, end parts of the gate electrode GE in a gate length direction are positioned on the semiconductor layer EP1.

Abstract translation: 半导体器件具有通过形成在基板上的栅极绝缘膜GI和源极/漏极半导体层EP1在基板上形成的栅电极GE。 半导体层EP1的上表面比栅电极GE下方的基板的上表面高。 并且，栅极电极GE的栅极长度方向的端部位于半导体层EP1上。

公开(公告)号：US09201440B2

公开(公告)日：2015-12-01

申请号：US14310731

申请日：2014-06-20

Applicant: Renesas Electronics Corporation

Inventor： Hideki Makiyama ,  Toshiaki Iwamatsu

IPC: G05F1/625

CPC classification number: H03K17/687 ,  G05F1/625 ,  H01L27/1203 ,  H01L29/78 ,  H03K2217/0018

Abstract: A semiconductor integrated circuit device has, as a current monitor circuit, a circuit in which n-channel type MISFETs are connected in series with each other. Based on a delay time of a speed monitor circuit in a state where a substrate bias is being applied to the p-channel type MISFETs, a first voltage value of a first substrate bias to be applied to the p-channel type MISFETs is determined. Next, based on a current flowing through an n-channel type MISFET in a state where the first substrate bias is being applied to the p-channel type MISFETs of the current monitor circuit and a second substrate bias is being applied to the n-channel type MISFETs of the current monitor circuit, a second voltage value of the second substrate bias to be applied to the n-channel type MISFETs is determined.

Abstract translation: 作为电流监视电路，半导体集成电路器件具有其中n沟道型MISFET彼此串联连接的电路。 基于将衬底偏压施加到p沟道型MISFET的状态下的速度监视器电路的延迟时间，确定要施加到p沟道型MISFET的第一衬底偏置的第一电压值。 接下来，基于在第一衬底偏压被施加到电流监视电路的p沟道型MISFET的状态下流过n沟道型MISFET的电流，并且第二衬底偏置被施加到n沟道 确定要施加到n沟道型MISFET的第二衬底偏置的第二电压值。