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    Semiconductor device and method of manufacturing the same
    2.
    发明授权
    Semiconductor device and method of manufacturing the same 有权
    半导体装置及其制造方法

    公开(公告)号：US09029237B2

    公开(公告)日：2015-05-12

    申请号：US13758802

    申请日：2013-02-04

    Applicant: Renesas Electronics Corporation

    Inventor： Mahito Sawada ,  Tatsunori Kaneoka ,  Katsuyuki Horita

    IPC: H01L21/76 ,  H01L21/762 ,  H01L21/02 ,  H01L21/3105

    CPC classification number: H01L29/0653 ,  H01L21/02164 ,  H01L21/02222 ,  H01L21/02282 ,  H01L21/02337 ,  H01L21/3105 ,  H01L21/76205 ,  H01L21/76229 ,  H01L27/088

    Abstract: To provide a semiconductor device provided with an element isolation structure capable of hindering an adverse effect on electric characteristics of a semiconductor element, and a method of manufacturing the same. The thickness of a first silicon oxide film left in a shallow trench isolation having a relatively narrow width is thinner than the first silicon oxide film left in a shallow trench isolation having a relatively wide width. A second silicon oxide film (an upper layer) having a relatively high compressive stress by an HDP-CVD method is more thickly laminated over the first silicon oxide film in a lower layer by a thinned thickness of the first silicon oxide film. The compressive stress of an element isolation oxide film finally formed in a shallow trench isolation having a relatively narrow width is more enhanced.

    Abstract translation: 提供一种具有能够阻碍对半导体元件的电特性的不利影响的元件隔离结构的半导体器件及其制造方法。 留在具有相对窄的宽度的浅沟槽隔离中的第一氧化硅膜的厚度比留在具有较宽宽度的浅沟槽隔离中的第一氧化硅膜薄。 通过HDP-CVD法具有相对高的压缩应力的第二氧化硅膜（上层）通过第一氧化硅膜的厚度较薄地层叠在下层的第一氧化硅膜上。 最终形成在具有相对窄的宽度的浅沟槽隔离中的元件隔离氧化膜的压缩应力被更强化。

    SOI SRAM having well regions with opposite conductivity
    5.
    发明授权
    SOI SRAM having well regions with opposite conductivity 有权
    具有相反导电性的阱区的SOI SRAM

    公开(公告)号：US09142567B2

    公开(公告)日：2015-09-22

    申请号：US14615336

    申请日：2015-02-05

    Applicant: Renesas Electronics Corporation

    Inventor： Katsuyuki Horita ,  Toshiaki Iwamatsu ,  Hideki Makiyama

    IPC: H01L27/12 ,  H01L27/092 ,  H01L27/11

    CPC classification number: H01L27/1203 ,  G11C11/412 ,  H01L21/2652 ,  H01L21/743 ,  H01L21/84 ,  H01L27/0207 ,  H01L27/092 ,  H01L27/1104 ,  H01L27/1108 ,  H01L29/78648

    Abstract: A semiconductor device with an SRAM memory cell having improved characteristics.Below an active region in which a driver transistor including a SRAM is placed, an n type back gate region surrounded by an element isolation region is provided via an insulating layer. It is coupled to the gate electrode of the driver transistor. A p well region is provided below the n type back gate region and at least partially extends to a position deeper than the element isolation region. It is fixed at a grounding potential. Such a configuration makes it possible to control the threshold potential of the transistor to be high when the transistor is ON and to be low when the transistor is OFF; and control so as not to apply a forward bias to the PN junction between the p well region and the n type back gate region.

    Abstract translation: 具有SRAM存储单元的具有改进特性的半导体器件。 在其中放置包括SRAM的驱动器晶体管的有源区域之下，经由绝缘层提供被元件隔离区域包围的n型背栅极区域。 它耦合到驱动晶体管的栅电极。 p型阱区域设置在n型背栅区域的下方，并且至少部分延伸到比元件隔离区域更深的位置。 它固定在接地电位。 这样的结构使得可以在晶体管导通时控制晶体管的阈值电位为高，而在晶体管截止时为低电平; 并且控制为不对p阱区域和n型背栅极区域之间的PN结施加正向偏压。

    Semiconductor device
    6.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US08975699B2

    公开(公告)日：2015-03-10

    申请号：US14495178

    申请日：2014-09-24

    Applicant: Renesas Electronics Corporation

    Inventor： Toshiaki Iwamatsu ,  Katsuyuki Horita ,  Hideki Makiyama

    IPC: H01L27/088 ,  H01L27/12 ,  H01L27/11

    CPC classification number: H01L27/1203 ,  H01L21/84 ,  H01L27/0207 ,  H01L27/1104 ,  H01L27/1108 ,  H01L27/1116 ,  H01L27/1207 ,  H01L29/78648

    Abstract: Improvements are achieved in the characteristics of a semiconductor device including SRAM memory cells. Under an active region in which an access transistor forming an SRAM is disposed, a p-type semiconductor region is disposed via an insulating layer such that the bottom portion and side portions thereof come in contact with an n-type semiconductor region. Thus, the p-type semiconductor region is pn-isolated from the n-type semiconductor region, and the gate electrode of the access transistor is coupled to the p-type semiconductor region. The coupling is achieved by a shared plug which is an indiscrete conductive film extending from over the gate electrode of the access transistor to over the p-type semiconductor region. As a result, when the access transistor is in an ON state, a potential in the p-type semiconductor region serving as a back gate simultaneously increases to allow an increase in an ON current for the transistor.

    Abstract translation: 在包括SRAM存储单元的半导体器件的特性中实现了改进。 在其中设置形成SRAM的存取晶体管的有源区域中，p型半导体区域经由绝缘层设置，使得其底部和侧部与n型半导体区域接触。 因此，p型半导体区域与n型半导体区域pn隔离，并且存取晶体管的栅电极耦合到p型半导体区域。 耦合是通过共享插头实现的，该共用插头是从存取晶体管的栅极电极延伸到p型半导体区域上的不连续的导电膜。 结果，当存取晶体管处于导通状态时，用作背栅的p型半导体区域中的电位同时增加，以允许晶体管的导通电流增加。

    Semiconductor device
    7.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US08872267B2

    公开(公告)日：2014-10-28

    申请号：US13675682

    申请日：2012-11-13

    Applicant: Renesas Electronics Corporation

    Inventor： Toshiaki Iwamatsu ,  Katsuyuki Horita ,  Hideki Makiyama

    IPC: H01L27/088 ,  H01L29/78 ,  H01L21/84 ,  H01L27/12 ,  H01L27/11 ,  H01L27/02 ,  H01L29/786

    CPC classification number: H01L27/1203 ,  H01L21/84 ,  H01L27/0207 ,  H01L27/1104 ,  H01L27/1108 ,  H01L27/1116 ,  H01L27/1207 ,  H01L29/78648

    Abstract: Improvements are achieved in the characteristics of a semiconductor device including SRAM memory cells. Under an active region in which an access transistor forming an SRAM is disposed, a p-type semiconductor region is disposed via an insulating layer such that the bottom portion and side portions thereof come in contact with an n-type semiconductor region. Thus, the p-type semiconductor region is pn-isolated from the n-type semiconductor region, and the gate electrode of the access transistor is coupled to the p-type semiconductor region. The coupling is achieved by a shared plug which is an indiscrete conductive film extending from over the gate electrode of the access transistor to over the p-type semiconductor region. As a result, when the access transistor is in an ON state, a potential in the p-type semiconductor region serving as a back gate simultaneously increases to allow an increase in an ON current for the transistor.

    Abstract translation: 在包括SRAM存储单元的半导体器件的特性中实现了改进。 在其中设置形成SRAM的存取晶体管的有源区域中，p型半导体区域经由绝缘层设置，使得其底部和侧部与n型半导体区域接触。 因此，p型半导体区域与n型半导体区域pn隔离，并且存取晶体管的栅电极耦合到p型半导体区域。 耦合是通过共享插头实现的，该共用插头是从存取晶体管的栅极电极延伸到p型半导体区域上的不连续的导电膜。 结果，当存取晶体管处于导通状态时，用作背栅的p型半导体区域中的电位同时增加，以允许晶体管的导通电流增加。

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